TH

Takehisa Hayashi

HI Hitachi: 48 patents #320 of 28,497Top 2%
HM Hitachi Maxell: 1 patents #659 of 1,211Top 55%
📍 Kokubunji, JP: #19 of 714 inventorsTop 3%
Overall (All Time): #56,877 of 4,157,543Top 2%
49
Patents All Time

Issued Patents All Time

Showing 1–25 of 49 patents

Patent #TitleCo-InventorsDate
7340552 Bus control system Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida 2008-03-04
7177970 Bus control system Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida 2007-02-13
6970912 Computer system having a plurality of computers each providing a shared storage access processing mechanism for controlling local/remote access to shared storage devices Hideki Murayama, Hiroshi Yashiro, Satoshi Yoshizawa, Kazuo Horikawa, Hiroshi Iwamoto +1 more 2005-11-29
6728258 Multi-processor system and its network Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Tetsuya Mochida, Masabumi Shibata +2 more 2004-04-27
6519667 Bus control system Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida 2003-02-11
6477560 Method and apparatus for controlling resource Hideki Murayama, Hiroshi Yashiro, Masahiro Kitano 2002-11-05
6341323 Information processing system Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida 2002-01-22
6335867 Apparatus for interconnecting logic boards Kenichi Ishibashi, Tsutomu Goto, Akira Yamagiwa, Tsuyoshi Watanabe 2002-01-01
6219738 Information processing system Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida 2001-04-17
6163464 Apparatus for interconnecting logic boards Kenichi Ishibashi, Tsutomu Goto, Akira Yamagiwa, Tsuyoshi Watanabe 2000-12-19
6128688 Bus control system Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida 2000-10-03
6108694 Memory disk sharing method and its implementing apparatus Hiroshi Yashiro, Hideki Murayama, Hirofumi Fujita, Masahiro Kitano 2000-08-22
6049221 Semiconductor integrated circuit system having function of automatically adjusting output resistance value Kenichi Ishibashi, Tsutomu Goto, Hideki Murayama, Akira Yamagiwa, Yasuhiro Ishii +2 more 2000-04-11
6011791 Multi-processor system and its network Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Tetsuya Mochida, Masabumi Shibata +2 more 2000-01-04
6005599 Video storage and delivery apparatus and system Mitsuo Asai, Yoshihiro Takiyasu, Koichi Shibata, Mikiko Sato, Atsushi Saito +1 more 1999-12-21
5941973 Bus control system incorporating the coupling of two split-transaction busses of different hierarchy Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida 1999-08-24
5935205 Computer system having a plurality of computers each providing a shared storage access processing mechanism for controlling local/remote access to shared storage devices Hideki Murayama, Hiroshi Yashiro, Satoshi Yoshizawa, Kazuo Horikawa, Hiroshi Iwamoto +1 more 1999-08-10
5936955 Network for mutually connecting computers and communicating method using such network Takeshi Aimoto, Hidenori Inouchi, Shoichi Murase, Shinichi Tanabe, Kazuhiro Hashimoto +6 more 1999-08-10
5881255 Bus control system incorporating the coupling of two split-transaction busses of different hierarchy Nobukazu Kondo, Seiji Kaneko, Koichi Okazawa, Hideaki Gemma, Tetsuya Mochida 1999-03-09
5872471 Simultaneous bidirectional transmission circuit Kenichi Ishibashi, Tsutomu Goto, Akira Yamagiwa, Toshitsugu Takekuma, Toshiro Takahashi +1 more 1999-02-16
5870594 Data transfer system and method Toshio Doi, Tetsuo Nakano 1999-02-09
5867541 Method and system for synchronizing data having skew Akira Tanaka, Kenichi Ishibashi, Akira Yamagiwa 1999-02-02
5835492 Network for mutually connecting computers and communicating method using such network Takeshi Aimoto, Hidenori Inouchi, Shoichi Murase, Shinichi Tanabe, Kazuhiro Hashimoto +6 more 1998-11-10
5794020 Data transfer apparatus fetching reception data at maximum margin of timing Akira Tanaka, Toshio Doi, Kenichi Ishibashi, Akira Yamagiwa 1998-08-11
5737589 Data transfer system and method including tuning of a sampling clock used for latching data Toshio Doi, Tetsuo Nakano 1998-04-07