Issued Patents All Time
Showing 25 most recent of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8397239 | Virtual computer systems and computer virtualization programs | Shinichi Kawamoto, Tatsuo Higuchi | 2013-03-12 |
| 7865899 | Virtual computer systems and computer virtualization programs | Shinichi Kawamoto, Tatsuo Higuchi | 2011-01-04 |
| 7313637 | Fabric and method for sharing an I/O device among virtual machines formed in a computer system | Tsuyoshi Tanaka, Keitaro Uehara, Yuji Tsushima, Daisuke Yoshida, Yoshinori Wakai | 2007-12-25 |
| 7290259 | Virtual computer system with dynamic resource reallocation | Tsuyoshi Tanaka, Toshiaki Tarui | 2007-10-30 |
| 7206818 | Shared memory multiprocessor system | Toshio Okochi, Toru Shonai, Naohiko Irie, Hideya Akashi | 2007-04-17 |
| 7117499 | Virtual computer systems and computer virtualization programs | Shinichi Kawamoto, Tatsuo Higuchi | 2006-10-03 |
| 6874053 | Shared memory multiprocessor performing cache coherence control and node controller therefor | Yoshiko Yasuda, Toru Shonai, Hideya Akashi, Yuji Tsushima, Keitaro Uehara | 2005-03-29 |
| 6789173 | Node controller for performing cache coherence control and memory-shared multiprocessor system | Tsuyoshi Tanaka, Hideya Akashi, Yuji Tsushima, Keitaro Uehara, Toru Shonai | 2004-09-07 |
| 6757788 | CACHE COHERENT CONTROL SYSTEM FOR NETWORK NODES ALLOWS CPU OR I/O DEVICE TO ACCESS TARGET BLOCK WITHOUT CACHE COHERENCE CONTROL, IF ASSOCIATED NODE HAS ACCESS RIGHT IN AN ACCESS RIGHT MEMORY TO TARGET BLOCK | Shinichi Kawamoto, Tatsuo Higuchi, Hiromitsu Maeda | 2004-06-29 |
| 6728258 | Multi-processor system and its network | Tetsuhiko Okada, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata +2 more | 2004-04-27 |
| 6640286 | Cache control system | Shinichi Kawamoto, Tatsuo Higuchi | 2003-10-28 |
| 6636926 | Shared memory multiprocessor performing cache coherence control and node controller therefor | Yoshiko Yasuda, Toru Shonai, Hideya Akashi, Yuji Tsushima, Keitaro Uehara | 2003-10-21 |
| 6591325 | Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer | Hideya Akashi, Yuji Tsushima, Keitaro Uehara, Toru Shonai, Tetsuhiko Okada +1 more | 2003-07-08 |
| 6587922 | Multiprocessor system | Tatsuo Higuchi, Shinichi Kawamoto | 2003-07-01 |
| 6516391 | Multiprocessor system and methods for transmitting memory access transactions for the same | Yuji Tsushima, Hideya Akashi, Keitaro Uehara, Toru Shonai, Tetsuhiko Okada +1 more | 2003-02-04 |
| 6298418 | Multiprocessor system and cache coherency control method | Shisei Fujiwara, Masabumi Shibata, Atsushi Nakajima, Naohiko Irie | 2001-10-02 |
| 6263405 | Multiprocessor system | Naohiko Irie, Tsuyoshi Tanaka, Masabumi Shibata, Atsushi Nakajima | 2001-07-17 |
| 6065111 | Processor with a processor-accessible cache for data received from outside of the processor | Tatsuo Higuchi | 2000-05-16 |
| 6049221 | Semiconductor integrated circuit system having function of automatically adjusting output resistance value | Kenichi Ishibashi, Takehisa Hayashi, Tsutomu Goto, Hideki Murayama, Akira Yamagiwa +2 more | 2000-04-11 |
| 6038644 | Multiprocessor system with partial broadcast capability of a cache coherent processing request | Naohiko Irie, Masabumi Shibata | 2000-03-14 |
| 6011791 | Multi-processor system and its network | Tetsuhiko Okada, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata +2 more | 2000-01-04 |
| 5842207 | Method for storing records of a distributed database by plural processors to provide a host processor with sorted records belonging to one of a plurality of key sections | Shinji Fujiwara, Yooichi Shintani, Mitsuru Nagasaka, Mikiko Suzuki | 1998-11-24 |
| 5825773 | Switching system for transferring broadcast packet held in broadcast buffer received from input port to output ports according to the state of each output port | Shin'ichi Shutoh, Junji Nakagoshi, Hiroyuki Chiba, Tatsuo Higuchi, Shigeo Takeuchi +2 more | 1998-10-20 |
| 5826049 | Partial broadcast method in parallel computer and a parallel computer suitable therefor | Yasuhiro Ogata, Junji Nakagoshi, Hiroyuki Chiba, Shinichi Shutoh, Tatsuo Higuchi +3 more | 1998-10-20 |
| 5754792 | Switch circuit comprised of logically split switches for parallel transfer of messages and a parallel processor system using the same | Shinichi Shutoh, Junji Nakagoshi, Shigeo Takeuchi, Teruo Tanaka | 1998-05-19 |