Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9858181 | Memory module having different types of memory mounted together thereon, and information processing device having memory module mounted therein | Yutaka Uematsu, Satoshi Muraoka, Hiroshi Kakita, Akio Idei, Yusuke Fukumura +10 more | 2018-01-02 |
| 9667697 | Direct memory access with conversion or reverse conversion of data | Nobuhiro Yokoi, Mutsumi Hosoya, Nagamasa Mizushima, Yoshihiro Yoshii | 2017-05-30 |
| 9658783 | DRAM having SDRAM interface and flash memory consolidated memory module | Satoshi Muraoka, Yutaka Uematsu, Hideki Osaka, Yuusuke Fukumura, Satoru Watanabe +8 more | 2017-05-23 |
| 9569144 | DRAM with SDRAM interface, and hybrid flash memory module | Yutaka Uematsu, Satoshi Muraoka, Hideki Osaka, Yuusuke Fukumura, Satoru Watanabe +8 more | 2017-02-14 |
| 9116858 | Direct memory access with conversion or reverse conversion of data | Nobuhiro Yokoi, Mutsumi Hosoya, Nagamasa Mizushima, Yoshihiro Yoshii | 2015-08-25 |
| 6728258 | Multi-processor system and its network | Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida +2 more | 2004-04-27 |
| 6298418 | Multiprocessor system and cache coherency control method | Shisei Fujiwara, Atsushi Nakajima, Naoki Hamanaka, Naohiko Irie | 2001-10-02 |
| 6263405 | Multiprocessor system | Naohiko Irie, Naoki Hamanaka, Tsuyoshi Tanaka, Atsushi Nakajima | 2001-07-17 |
| 6049221 | Semiconductor integrated circuit system having function of automatically adjusting output resistance value | Kenichi Ishibashi, Takehisa Hayashi, Tsutomu Goto, Hideki Murayama, Akira Yamagiwa +2 more | 2000-04-11 |
| 6038644 | Multiprocessor system with partial broadcast capability of a cache coherent processing request | Naohiko Irie, Naoki Hamanaka | 2000-03-14 |
| 6011791 | Multi-processor system and its network | Tetsuhiko Okada, Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida +2 more | 2000-01-04 |
| 5987571 | Cache coherency control method and multi-processor system using the same | Atsushi Nakajima, Shisei Fujiwara | 1999-11-16 |
| 5584004 | Data processing system having subsystems connected by busses | Takeshi Aimoto, Akira Ishiyama, Hidenori Kosugi | 1996-12-10 |
| 5442755 | Multi-processor system with lock address register in each processor for storing lock address sent to bus by another processor | — | 1995-08-15 |
| 5353428 | Information processing apparatus in which a cache memory can be operated in both store-in and store-through modes | — | 1994-10-04 |
| 5136702 | Buffer storage control method and apparatus | — | 1992-08-04 |
| 5008817 | Method and apparatus for transferring addresses and information in a buffer memory and a common main storage device | Akira Ishiyama, Takeshi Takemoto | 1991-04-16 |