| RE41589 |
Memory system performing fast access to a memory location by omitting the transfer of a redundant address |
Osamu Nishii, Nobuyuki Hayashi, Noriharu Hiratsuka, Hiroshi Takeda |
2010-08-24 |
| 6728258 |
Multi-processor system and its network |
Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata +2 more |
2004-04-27 |
| 6591325 |
Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer |
Hideya Akashi, Yuji Tsushima, Keitaro Uehara, Naoki Hamanaka, Toru Shonai +1 more |
2003-07-08 |
| 6516391 |
Multiprocessor system and methods for transmitting memory access transactions for the same |
Yuji Tsushima, Hideya Akashi, Keitaro Uehara, Naoki Hamanaka, Toru Shonai +1 more |
2003-02-04 |
| 6292867 |
Data processing system |
Osamu Nishii, Nobuyuki Hayashi, Noriharu Hiratsuka, Hiroshi Takeda |
2001-09-18 |
| 6219735 |
Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement |
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Kazuhiko Komori, Koichi Okazawa |
2001-04-17 |
| 6154807 |
Memory system performing fast access to a memory location by omitting the transfer of a redundant address |
Osamu Nishii, Nobuyuki Hayashi, Noriharu Hiratsuka, Hiroshi Takeda |
2000-11-28 |
| 6047345 |
Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment |
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Kazuhiko Komori, Koichi Okazawa |
2000-04-04 |
| 6011791 |
Multi-processor system and its network |
Naoki Hamanaka, Naohiko Irie, Takehisa Hayashi, Tetsuya Mochida, Masabumi Shibata +2 more |
2000-01-04 |
| 5873122 |
Memory system performing fast access to a memory location by omitting transfer of a redundant address |
Osamu Nishii, Nobuyuki Hayashi, Noriharu Hiratsuka, Hiroshi Takeda |
1999-02-16 |
| 5774679 |
Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement |
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Kazuhiko Komori, Koichi Okazawa |
1998-06-30 |
| 5678062 |
Input/output control method and data processor |
Hideki Murayama, Takehisa Hayashi, Atsushi Ugajin, Yasuhiro Ishii, Masahiro Kitano |
1997-10-14 |
| 5657458 |
Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment |
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Kazuhiko Komori, Koichi Okazawa |
1997-08-12 |
| 5652858 |
Method for prefetching pointer-type data structure and information processing apparatus therefor |
Osamu Nishii, Hiroshi Takeda |
1997-07-29 |
| 5604874 |
Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment |
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Kazuhiko Komori, Koichi Okazawa |
1997-02-18 |
| 5590290 |
Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgement |
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Kazuhiko Komori, Koichi Okazawa |
1996-12-31 |
| 5428753 |
Method for controlling a bus to progress transfer cycles without inserting a cycle for acknowledgment |
Nobukazu Kondo, Seiji Kaneko, Hideaki Gemma, Kazuhiko Komori, Koichi Okazawa |
1995-06-27 |
| 5408625 |
Microprocessor capable of decoding two instructions in parallel |
Susumu Narita, Fumio Arakawa, Kunio Uchiyama |
1995-04-18 |
| 5220670 |
Microprocessor having ability to carry out logical operation on internal bus |
Fumio Arakawa, Ikuya Kawasaki |
1993-06-15 |
| 5148532 |
Pipeline processor with prefetch circuit |
Susumu Narita, Makoto Hanawa, Tadahiko Nishimukai |
1992-09-15 |