HA

Hideya Akashi

HI Hitachi: 15 patents #2,636 of 28,497Top 10%
Overall (All Time): #326,734 of 4,157,543Top 8%
15
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
7206818 Shared memory multiprocessor system Toshio Okochi, Toru Shonai, Naoki Hamanaka, Naohiko Irie 2007-04-17
6993633 Computer system utilizing speculative read requests to cache memory Tadayuki Sakakibara, Isao Ohara, Yuji Tsushima, Satoshi Muraoka 2006-01-31
6874053 Shared memory multiprocessor performing cache coherence control and node controller therefor Yoshiko Yasuda, Naoki Hamanaka, Toru Shonai, Yuji Tsushima, Keitaro Uehara 2005-03-29
6839806 Cache system with a cache tag memory and a cache tag buffer Yoshiki Murakami, Masaru Koyanagi 2005-01-04
6789173 Node controller for performing cache coherence control and memory-shared multiprocessor system Tsuyoshi Tanaka, Yuji Tsushima, Keitaro Uehara, Naoki Hamanaka, Toru Shonai 2004-09-07
6636926 Shared memory multiprocessor performing cache coherence control and node controller therefor Yoshiko Yasuda, Naoki Hamanaka, Toru Shonai, Yuji Tsushima, Keitaro Uehara 2003-10-21
6606688 Cache control method and cache controller Masaru Koyanagi, Disuke Yamane, Yuji Tsushima, Tadayuki Sakakibara 2003-08-12
6591325 Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointer Yuji Tsushima, Keitaro Uehara, Naoki Hamanaka, Toru Shonai, Tetsuhiko Okada +1 more 2003-07-08
6546471 Shared memory multiprocessor performing cache coherency Toshiaki Tarui, Koichi Okazawa, Yasuyuki Okada, Toru Shonai, Toshio Okochi 2003-04-08
6516391 Multiprocessor system and methods for transmitting memory access transactions for the same Yuji Tsushima, Keitaro Uehara, Naoki Hamanaka, Toru Shonai, Tetsuhiko Okada +1 more 2003-02-04
6438653 Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor system Toshio Okochi, Toru Shonai, Masamori Kashiyama 2002-08-20
6295579 Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas Naonobu Sukegawa, Tshiaki Tarui, Hiroaki Fujii 2001-09-25
6119150 Message passing distributed shared memory system that eliminates unnecessary software controlled cache flushes or purges Hiroaki Fujii, Tadaaki Isobe, Makoto Koga 2000-09-12
6088770 Shared memory multiprocessor performing cache coherency Toshiaki Tarui, Koichi Okazawa, Yasuyuki Okada, Toru Shonai, Toshio Okochi 2000-07-11
5778429 Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas Naonobu Sukegawa, Tshiaki Tarui, Hiroaki Fujii 1998-07-07