Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8296746 | Optimum code generation method and compiler device for multiprocessor | Koichi Takayama | 2012-10-23 |
| 8234453 | Processor having a cache memory which is comprised of a plurality of large scale integration | — | 2012-07-31 |
| 8108629 | Method and computer for reducing power consumption of a memory | Masaaki Shimizu | 2012-01-31 |
| 7958508 | Method of power-aware job management and computer system | Masaaki Shimizu | 2011-06-07 |
| 7895399 | Computer system and control method for controlling processor execution of a prefetech command | Aki Tomita | 2011-02-22 |
| 7739530 | Method and program for generating execution code for performing parallel processing | Koichi Takayama | 2010-06-15 |
| 7366814 | Heterogeneous multiprocessor system and OS configuration method thereof | Masaaki Shimizu | 2008-04-29 |
| 7293092 | Computing system and control method | — | 2007-11-06 |
| 7191294 | Method for synchronizing processors in a multiprocessor system | Tomohiro Nakamura | 2007-03-13 |
| 7159079 | Multiprocessor system | — | 2007-01-02 |
| 7155540 | Data communication method in shared memory multiprocessor system | Tomohiro Nakamura | 2006-12-26 |
| 6466988 | Multiprocessor synchronization and coherency control system | Kouki Uwano, Shigeko Hashimoto, Masakazu Fukagawa, Eiki Kamada | 2002-10-15 |
| 6335903 | Memory system | Tetsuhito Nakamura, Tsuguo Matsuura, Masanao Ito | 2002-01-01 |
| 6295579 | Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas | Tshiaki Tarui, Hiroaki Fujii, Hideya Akashi | 2001-09-25 |
| 6263406 | Parallel processor synchronization and coherency control method and system | Kohki Uwano, Shigeko Hashimoto, Tadaaki Isobe, Miki Miyaki, Tatsuya Ichiki | 2001-07-17 |
| 5978830 | Multiple parallel-job scheduling method and apparatus | Akihiro Nakaya, Takashi Nishikado, Hiroyuki Kumazaki, Kei Nakajima, Masakazu Fukagawa | 1999-11-02 |
| 5978894 | Method of interprocessor data transfer using a network, virtual addresses and paging, a buffer, flags, data transfer status information and user accessible storage areas in main memory | Masanao Ito, Yoshiko Tamaki | 1999-11-02 |
| 5968135 | Processing instructions up to load instruction after executing sync flag monitor instruction during plural processor shared memory store/load access synchronization | Yasuhiro Teramoto, Toshimitsu Andoh, Tadaaki Isobe, Yuko ISHIBASHI | 1999-10-19 |
| 5898883 | Memory access mechanism for a parallel processing computer system with distributed shared memory | Hiroaki Fujii, Toshiaki Tarui | 1999-04-27 |
| 5778429 | Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areas | Tshiaki Tarui, Hiroaki Fujii, Hideya Akashi | 1998-07-07 |
| 5606686 | Access control method for a shared main memory in a multiprocessor based upon a directory held at a storage location of data in the memory after reading data to a processor | Toshiaki Tarui, Hiroaki Fujii, Katsuyoshi Kitai | 1997-02-25 |