| 6560676 |
Cache memory system having a replace way limitation circuit and a processor |
Akira Nishimoto, Akira Hirono |
2003-05-06 |
| 6466988 |
Multiprocessor synchronization and coherency control system |
Naonobu Sukegawa, Kouki Uwano, Shigeko Hashimoto, Masakazu Fukagawa |
2002-10-15 |
| 5931895 |
Floating-point arithmetic processing apparatus |
Hiromichi Yamada, Fumio Murabayashi, Tatsumi Yamauchi, Noriyasu Ido, Yoshikazu Kiyoshige +1 more |
1999-08-03 |
| 5922068 |
Information processing system and information processing method for executing instructions in parallel |
Yooichi Shintani, Kazunori Kuriyama, Tohru Shonai, Kiyoshi Inoue |
1999-07-13 |
| 5845321 |
Store buffer apparatus with two store buffers to increase throughput of a store operation |
Motohisa Ito, Toshiko Isobe, Kei Yamamoto, Katsutoshi Uehara |
1998-12-01 |
| 5742782 |
Processing apparatus for executing a plurality of VLIW threads in parallel |
Motohisa Ito |
1998-04-21 |
| 5671382 |
Information processing system and information processing method for executing instructions in parallel |
Yooichi Shintani, Kazunori Kuriyama, Tohru Shonai, Kiyoshi Inoue |
1997-09-23 |
| 5600819 |
Memory with sequential data transfer scheme |
Satoshi Oguni |
1997-02-04 |
| 5075849 |
Information processor providing enhanced handling of address-conflicting instructions during pipeline processing |
Kazunori Kuriyama, Yooichi Shintani, Tohru Shonai, Kiyoshi Inoue |
1991-12-24 |
| 4942525 |
Data processor for concurrent executing of instructions by plural execution units |
Yooichi Shintani, Kazunori Kuriyama, Tohru Shonai, Kiyoshi Inoue |
1990-07-17 |
| 4928226 |
Data processor for parallelly executing conflicting instructions |
Yooichi Shintani, Kazunori Kuriyama, Tohru Shonai, Kiyoshi Inoue |
1990-05-22 |
| 4858105 |
Pipelined data processor capable of decoding and executing plural instructions in parallel |
Kazunori Kuriyama, Yooichi Shintani, Akira Yamaoka, Tohru Shonai, Kiyoshi Inoue |
1989-08-15 |
| 4831515 |
Information processing apparatus for determining sequence of parallel executing instructions in response to storage requirements thereof |
Yooichi Shintani, Tohru Shonai, Shigeo Takeuchi |
1989-05-16 |
| 4760520 |
Data processor capable of executing instructions under prediction |
Yooichi Shintani, Tohru Shonai, Shigeo Takeuchi |
1988-07-26 |
| 4752873 |
Data processor having a plurality of operating units, logical registers, and physical registers for parallel instructions execution |
Tohru Shonai, Shigeo Takeuchi |
1988-06-21 |