Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5922068 | Information processing system and information processing method for executing instructions in parallel | Kazunori Kuriyama, Tohru Shonai, Eiki Kamada, Kiyoshi Inoue | 1999-07-13 |
| 5842207 | Method for storing records of a distributed database by plural processors to provide a host processor with sorted records belonging to one of a plurality of key sections | Shinji Fujiwara, Mitsuru Nagasaka, Naoki Hamanaka, Mikiko Suzuki | 1998-11-24 |
| 5721865 | Information processing apparatus with prefetch control for prefetching data structure from memory through cache memory | Yoshikazu Tanaka, Naohiko Irie, William S. Worley, Jr., B. Ramakrishna Rau, Rajiv Gupta +1 more | 1998-02-24 |
| 5671382 | Information processing system and information processing method for executing instructions in parallel | Kazunori Kuriyama, Tohru Shonai, Eiki Kamada, Kiyoshi Inoue | 1997-09-23 |
| 5515531 | Parallel database processing system and retrieval method using secondary key | Shinji Fujiwara, Mitsuru Nagasaka | 1996-05-07 |
| 5075849 | Information processor providing enhanced handling of address-conflicting instructions during pipeline processing | Kazunori Kuriyama, Tohru Shonai, Eiki Kamada, Kiyoshi Inoue | 1991-12-24 |
| 4942525 | Data processor for concurrent executing of instructions by plural execution units | Kazunori Kuriyama, Tohru Shonai, Eiki Kamada, Kiyoshi Inoue | 1990-07-17 |
| 4928226 | Data processor for parallelly executing conflicting instructions | Eiki Kamada, Kazunori Kuriyama, Tohru Shonai, Kiyoshi Inoue | 1990-05-22 |
| 4916606 | Pipelined parallel data processing apparatus for directly transferring operand data between preceding and succeeding instructions | Akira Yamaoka, Kenichi Wada, Kazunori Kuriyama | 1990-04-10 |
| 4858105 | Pipelined data processor capable of decoding and executing plural instructions in parallel | Kazunori Kuriyama, Akira Yamaoka, Tohru Shonai, Eiki Kamada, Kiyoshi Inoue | 1989-08-15 |
| 4831515 | Information processing apparatus for determining sequence of parallel executing instructions in response to storage requirements thereof | Eiki Kamada, Tohru Shonai, Shigeo Takeuchi | 1989-05-16 |
| 4760520 | Data processor capable of executing instructions under prediction | Tohru Shonai, Eiki Kamada, Shigeo Takeuchi | 1988-07-26 |
| 4739470 | Data processing system | Kenichi Wada, Tsuguo Shimizu, Akira Yamaoka | 1988-04-19 |
| 4736288 | Data processing device | Tohru Shonai, Shigeo Takeuchi | 1988-04-05 |
| 4679140 | Data processor with control of the significant bit lengths of general purpose registers | Shizuo Gotou, Toyohiko Kagimasa, Seiichi Yoshizumi | 1987-07-07 |
| 4618926 | Buffer storage control system | Kanji Kubo, Kenichi Wada | 1986-10-21 |
| 4608671 | Buffer storage including a swapping circuit | Tsuguo Shimizu, Kenichi Wada, Akira Yamaoka | 1986-08-26 |
| 4541047 | Pipelined data processing system | Kenichi Wada, Tsuguo Shimizu, Akira Yamaoka | 1985-09-10 |