Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6507809 | Method and system for simulating performance of a computer system | TAISEI YOSHINO, Isao Watanabe | 2003-01-14 |
| 6044450 | Processor for VLIW instruction | Yuji Tsushima, Yoshikazu Tanaka, Masanao Ito, Kentaro Shimada, Yonetaro Totsuka +1 more | 2000-03-28 |
| 5978894 | Method of interprocessor data transfer using a network, virtual addresses and paging, a buffer, flags, data transfer status information and user accessible storage areas in main memory | Naonobu Sukegawa, Masanao Ito | 1999-11-02 |
| 5872989 | Processor having a register configuration suited for parallel execution control of loop processing | Yuji Tsushima, Yoshikazu Tanaka | 1999-02-16 |
| 5857110 | Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors | Tadayuki Sakakibara, Teruo Tanaka, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto +1 more | 1999-01-05 |
| 5809539 | Processor system having address allocation and address lock capability adapted for a memory comprised of synchronous DRAMs | Tadayuki Sakakibara, Teruo Tanaka | 1998-09-15 |
| 5754876 | Data processor system for preloading/poststoring data arrays processed by plural processors in a sharing manner | Teruo Tanaka, Tadayuki Sakakibaraa | 1998-05-19 |
| 5617575 | Interprocessor priority control system for multivector processor | Tadayuki Sakakibara, Teruo Tanaka, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto +1 more | 1997-04-01 |
| 5590353 | Vector processor adopting a memory skewing scheme for preventing degradation of access performance | Tadayuki Sakakibara, Teruo Tanaka, Katsuyoshi Kitai, Yasuhiro Inagami | 1996-12-31 |
| 5530881 | Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs | Yasuhiro Inagami, Teruo Tanaka, Katsuyoshi Kitai, Tadayuki Sakakibara | 1996-06-25 |
| 5506980 | Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory | Yasuhiro Inagami, Katsuyoshi Kitai, Teruo Tanaka, Tadayuki Sakakibara | 1996-04-09 |
| 5440750 | Information processing system capable of executing a single instruction for watching and waiting for writing of information for synchronization by another processor | Katsuyoshi Kitai, Yasuhiro Inagami, Yoshikazu Tanaka | 1995-08-08 |
| 5437043 | Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers | Hiroaki Fujii, Naoki Hamanaka, Teruo Tanaka, Yasuhiro Inagami | 1995-07-25 |
| 5396603 | Data processor having resources and execution start control for starting execution of succeeding instruction in resource before completion of preceding instruction | Shigeko Yazawa, Yasuhiro Inagami, Katsuyoshi Kitai | 1995-03-07 |
| 5392443 | Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data | Tadayuki Sakakibara, Katsuyoshi Kitai, Yasuhiro Inagami, Teruo Tanaka, Tadaaki Isobe +2 more | 1995-02-21 |
| 5339429 | Parallel processing system and compiling method used therefor | Teruo Tanaka, Yasuhiro Inagami, Tadayuki Sakakibara, Katsuyoshi Kitai | 1994-08-16 |
| 5193186 | Processor system for executing processes in parallel under multitask, control method of waiting for event of process | Katsuyoshi Kitai, Yasuhiro Inagami, Yoshikazu Tanaka | 1993-03-09 |
| 5109499 | Vector multiprocessor system which individually indicates the data element stored in common vector register | Yasuhiro Inagami, Katsuyoshi Kitai | 1992-04-28 |
| 4992936 | Address translation method and apparatus therefor | Hisashi Katada, Yasuhiro Inagami, Shigeo Nagashima | 1991-02-12 |
| 4881168 | Vector processor with vector data compression/expansion capability | Yasuhiro Inagami, Takayuki Nakagawa, Shigeo Nagashima | 1989-11-14 |