Issued Patents All Time
Showing 25 most recent of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6502136 | EXCLUSIVE CONTROL METHOD WITH EACH NODE CONTROLLING ISSUE OF AN EXCLUSIVE USE REQUEST TO A SHARED RESOURCE, A COMPUTER SYSTEM THEREFOR AND A COMPUTER SYSTEM WITH A CIRCUIT FOR DETECTING WRITING OF AN EVENT FLAG INTO A SHARED MAIN STORAGE | Tatsuo Higuchi, Toshiaki Tarui, Katsuyoshi Kitai, Shigeo Takeuchi, Tatsuru Toba +1 more | 2002-12-31 |
| 6330604 | Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage | Tatsuo Higuchi, Toshiaki Tarui, Katsuyoshi Kitai, Shigeo Takeuchi, Tatsuru Toba +1 more | 2001-12-11 |
| 6049839 | Data processor with multiple register queues | Hiroaki Fujii, Shigeo Takeuchi | 2000-04-11 |
| 5857110 | Priority control with concurrent switching of priorities of vector processors, for plural priority circuits for memory modules shared by the vector processors | Tadayuki Sakakibara, Teruo Tanaka, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto +1 more | 1999-01-05 |
| 5774731 | Exclusive control method with each node controlling issue of an exclusive use request to a shared resource, a computer system therefor and a computer system with a circuit for detecting writing of an event flag into a shared main storage | Tatsuo Higuchi, Toshiaki Tarui, Katsuyoshi Kitai, Shigeo Takeuchi, Tatsuru Toba +1 more | 1998-06-30 |
| 5729723 | Data processing unit | Hideo Wada, Katsumi Takeda, Hiroaki Fujii | 1998-03-17 |
| 5617575 | Interprocessor priority control system for multivector processor | Tadayuki Sakakibara, Teruo Tanaka, Katsuyoshi Kitai, Tadaaki Isobe, Shigeko Hashimoto +1 more | 1997-04-01 |
| 5590353 | Vector processor adopting a memory skewing scheme for preventing degradation of access performance | Tadayuki Sakakibara, Teruo Tanaka, Yoshiko Tamaki, Katsuyoshi Kitai | 1996-12-31 |
| 5581721 | Data processing unit which can access more registers than the registers indicated by the register fields in an instruction | Hideo Wada, Katsumi Takeda, Hiroaki Fujii | 1996-12-03 |
| 5530881 | Vector processing apparatus for processing different instruction set architectures corresponding to mingled-type programs and separate-type programs | Teruo Tanaka, Yoshiko Tamaki, Katsuyoshi Kitai, Tadayuki Sakakibara | 1996-06-25 |
| 5506980 | Method and apparatus for parallel processing of a large data array utilizing a shared auxiliary memory | Yoshiko Tamaki, Katsuyoshi Kitai, Teruo Tanaka, Tadayuki Sakakibara | 1996-04-09 |
| 5440750 | Information processing system capable of executing a single instruction for watching and waiting for writing of information for synchronization by another processor | Katsuyoshi Kitai, Yoshiko Tamaki, Yoshikazu Tanaka | 1995-08-08 |
| 5437043 | Information processing apparatus having a register file used interchangeably both as scalar registers of register windows and as vector registers | Hiroaki Fujii, Naoki Hamanaka, Teruo Tanaka, Yoshiko Tamaki | 1995-07-25 |
| 5396603 | Data processor having resources and execution start control for starting execution of succeeding instruction in resource before completion of preceding instruction | Yoshiko Tamaki, Shigeko Yazawa, Katsuyoshi Kitai | 1995-03-07 |
| 5392443 | Vector processor with a memory assigned with skewed addresses adapted for concurrent fetching of a number of vector elements belonging to the same vector data | Tadayuki Sakakibara, Katsuyoshi Kitai, Yoshiko Tamaki, Teruo Tanaka, Tadaaki Isobe +2 more | 1995-02-21 |
| 5349653 | Apparatus for converting parallel bits of an electrical data signal into serial bits of an optical data signal utilizing an optical time delay | Hiroshi Kurokawa, Yasushi Takahashi | 1994-09-20 |
| 5339429 | Parallel processing system and compiling method used therefor | Teruo Tanaka, Yoshiko Tamaki, Tadayuki Sakakibara, Katsuyoshi Kitai | 1994-08-16 |
| 5193186 | Processor system for executing processes in parallel under multitask, control method of waiting for event of process | Yoshiko Tamaki, Katsuyoshi Kitai, Yoshikazu Tanaka | 1993-03-09 |
| 5109499 | Vector multiprocessor system which individually indicates the data element stored in common vector register | Yoshiko Tamaki, Katsuyoshi Kitai | 1992-04-28 |
| 5073970 | Vector processing apparatus allowing succeeding vector instruction chain processing upon completion of decoding of a preceding vector instruction chain | Tamoo Aoyama, Hiroshi Nurayama | 1991-12-17 |
| 4992936 | Address translation method and apparatus therefor | Hisashi Katada, Yoshiko Tamaki, Shigeo Nagashima | 1991-02-12 |
| 4910667 | Vector processor with vector buffer memory for read or write of vector data between vector storage and operation unit | Teruo Tanaka, Koichiro Omoda, Takayuki Nakagawa, Mamoru Sugie, Shigeo Nagashima | 1990-03-20 |
| 4881168 | Vector processor with vector data compression/expansion capability | Takayuki Nakagawa, Yoshiko Tamaki, Shigeo Nagashima | 1989-11-14 |
| 4825361 | Vector processor for reordering vector data during transfer from main memory to vector registers | Koichiro Omoda, Shunichi Torii, Shigeo Nagashima, Takayuki Nakagawa | 1989-04-25 |
| 4803620 | Multi-processor system responsive to pause and pause clearing instructions for instruction execution control | Takayuki Nakagawa, Shigeo Nagashima | 1989-02-07 |