Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9501592 | Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language | Aaron Mitchell Spratt, William S. Cranston, Chandrashekar L. Chetput | 2016-11-22 |
| 9058440 | Method and mechanism for verifying and simulating power aware mixed-signal electronic designs | — | 2015-06-16 |
| 8949753 | Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language | Aaron Mitchell Spratt, William S. Cranston, Chandrashekar L. Chetput | 2015-02-03 |
| 8732630 | Methods, systems, and articles of manufacture for implementing analog behavioral modeling and IP integration using systemverilog hardware description language | Aaron Mitchell Spratt, William S. Cranston, Chandrashekar L. Chetput | 2014-05-20 |
| 8640073 | Analog/digital partitioning of circuit designs for simulation | Chandrashekar L. Chetput, Iyengar Venkatachary Srinivasan | 2014-01-28 |
| 8504346 | Method and mechanism for performing mixed-signal simulation of electronic designs having complex digital signal types or models | Chandrashekar L. Chetput | 2013-08-06 |
| 8448116 | Analog/digital partitioning of circuit designs for simulation | Chandrashekar L. Chetput, Srinivasan Iyengar | 2013-05-21 |
| 8296699 | Method and system for supporting both analog and digital signal traffic on a single hierarchical connection for mixed-signal verification | Chandrashekar L. Chetput | 2012-10-23 |
| 8255191 | Using real value models in simulation of analog and mixed-signal systems | Chandrashekar L. Chetput, Timothy Martin O'Leary | 2012-08-28 |
| 8234617 | Method and system for re-using digital assertions in a mixed signal design | Chandrashekar L. Chetput, Donald J. O'Riordan | 2012-07-31 |
| 7979262 | Method for verifying connectivity of electrical circuit components | Srinivasan Iyengar, Chandrashekar L. Chetput | 2011-07-12 |
| 7797659 | Analog/digital partitioning of circuit designs for simulation | Chandrashekar L. Chetput, Srinivasan Iyengar | 2010-09-14 |
| 7523424 | Method and system for representing analog connectivity in hardware description language designs | Scott Cranston, Peter Frey | 2009-04-21 |
| 7251795 | Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design | Prasenjit Biswas, Ramesh S. Mayiladuthurai, Chandrashekar L. Chetput | 2007-07-31 |