Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7260792 | Modeling a mixed-language mixed-signal design | Chandrashekar L. Chetput, Prasenjit Biswas | 2007-08-21 |
| 7251795 | Connecting verilog-AMS and VHDL-AMS components in a mixed-language mixed-signal design | Prasenjit Biswas, Chandrashekar L. Chetput, Abhijeet Kolpekwar | 2007-07-31 |