Issued Patents All Time
Showing 1–6 of 6 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6078941 | Computational structure having multiple stages wherein each stage includes a pair of adders and a multiplexing circuit capable of operating in parallel | Roney S. Wong, Seungyoon Peter-Song | 2000-06-20 |
| 5993051 | Combined leading one and leading zero anticipator | Ted T. Nguyen | 1999-11-30 |
| 5958000 | Two-bit booth multiplier with reduced data path width | — | 1999-09-28 |
| 5943251 | Adder which handles multiple data with different data types | Le Trong Nguyen | 1999-08-24 |
| 5928316 | Fused floating-point multiply-and-accumulate unit with carry correction | Roney S. Wong | 1999-07-27 |
| 5796644 | Floating-point multiply-and-accumulate unit with classes for alignment and normalization | — | 1998-08-18 |