Issued Patents All Time
Showing 201–225 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8755234 | Temperature based compensation during verify operations for non-volatile storage | Ken Oowada, Gerrit Jan Hemink, Man Lung Mui, Hao Thai Nguyen, Seungpil Lee +2 more | 2014-06-17 |
| 8670285 | Reducing weak-erase type read disturb in 3D non-volatile memory | Man Lung Mui, Hitoshi Miwa | 2014-03-11 |
| 8582381 | Temperature based compensation during verify operations for non-volatile storage | Ken Oowada, Gerrit Jan Hemink, Man Lung Mui, Hao Thai Nguyen, Seungpil Lee +2 more | 2013-11-12 |
| 8472257 | Nonvolatile memory and method for improved programming with reduced verify | Ken Oowada, Cynthia Hsu | 2013-06-25 |
| 8456915 | Programming non-volatile storage with fast bit detection and verify skip | Changyuan Chen, Jeffrey W. Lutze, Hua-Ling Cynthia Hsu | 2013-06-04 |
| 8456911 | Intelligent shifting of read pass voltages for non-volatile storage | Jiahui Yuan, Charles See Yeung Kwong | 2013-06-04 |
| 8315093 | Selective memory cell program and erase | Tien-Chien Kuo, Gerrit Jan Hemink | 2012-11-20 |
| 8218366 | Programming non-volatile storage including reducing impact from other memory cells | Shih-Chung Lee, Ken Oowada | 2012-07-10 |
| 8208310 | Mitigating channel coupling effects during sensing of non-volatile storage elements | Yan Li, Cynthia Hsu | 2012-06-26 |
| 8174895 | Programming non-volatile storage with fast bit detection and verify skip | Changyuan Chen, Jeffrey W. Lutze, Hua-Ling Cynthia Hsu | 2012-05-08 |
| 8144511 | Selective memory cell program and erase | Tien-Chien Kuo, Gerrit Jan Hemink | 2012-03-27 |
| 8130551 | Extra dummy erase pulses after shallow erase-verify to avoid sensing deep erased threshold voltage | Ken Oowada, Deepanshu Dutta | 2012-03-06 |
| 8116140 | Saw-shaped multi-pulse programming for program noise reduction in memory | Yupin Fong, Gerrit Jan Hemink | 2012-02-14 |
| 8081514 | Partial speed and full speed programming for non-volatile memory using floating bit lines | Man Lung Mui, Binh Lee, Deepanshu Dutta | 2011-12-20 |
| 8045384 | Reduced programming pulse width for enhanced channel boosting in non-volatile storage | Jeffrey W. Lutze | 2011-10-25 |
| 8036044 | Dynamically adjustable erase and program levels for non-volatile memory | Jun Wan | 2011-10-11 |
| 7995394 | Program voltage compensation with word line bias change to suppress charge trapping in memory | Toru Ishigaki, Ken Oowada | 2011-08-09 |
| 7961511 | Hybrid programming methods and systems for non-volatile memory storage elements | Dana Lee, Changyuan Chen, Jeffrey W. Lutze | 2011-06-14 |
| 7916533 | Forecasting program disturb in memory by detecting natural threshold voltage distribution | Cynthia Hsu | 2011-03-29 |
| 7898864 | Read operation for memory with compensation for coupling based on write-erase cycles | — | 2011-03-01 |
| 7876611 | Compensating for coupling during read operations in non-volatile storage | Deepanshu Dutta, Jeffrey W. Lutze, Henry Chin, Toru Ishigaki | 2011-01-25 |
| 7800956 | Programming algorithm to reduce disturb with minimal extra time penalty | Dana Lee, Deepanshu Dutta | 2010-09-21 |
| 7796430 | Non-volatile memory using multiple boosting modes for reduced program disturb | Jeffrey W. Lutze | 2010-09-14 |
| 7719902 | Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage | Man Lung Mui, Jeffrey W. Lutze, Shinji Sato, Gerrit Jan Hemink | 2010-05-18 |
| 7706189 | Non-volatile storage system with transitional voltage during programming | Jeffrey W. Lutze, Dana Lee | 2010-04-27 |