Issued Patents All Time
Showing 176–200 of 240 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8988937 | Pre-charge during programming for 3D memory using gate-induced drain leakage | Mohan Dunga, Wendy Ou | 2015-03-24 |
| 8988941 | Select transistor tuning | Chris Avila, Man Lung Mui | 2015-03-24 |
| 8982626 | Program and read operations for 3D non-volatile memory based on memory hole diameter | Wendy Ou, Man Lung Mui, Masaaki Higashitani | 2015-03-17 |
| 8982637 | Vread bias allocation on word lines for read disturb reduction in 3D non-volatile memory | Chenfeng Zhang, Wendy Ou, Seung Yu, Masaaki Higashitani | 2015-03-17 |
| 8971119 | Select transistor tuning | Chris Avila, Man Lung Mui | 2015-03-03 |
| 8964467 | Systems and methods for partial page programming of multi level cells | Gautam Dusija, Chris Avila, Deepak Raghu, Man Lung Mui, Alexander Kwok-Tung Mak +1 more | 2015-02-24 |
| 8964480 | Detecting programmed word lines based on NAND string current | Man Lung Mui, Chris Avila | 2015-02-24 |
| 8966330 | Bad block reconfiguration in nonvolatile memory | Deepak Raghu, Gautam Dusija, Chris Avila, Man Lung Mui | 2015-02-24 |
| 8964473 | Select gate materials having different work functions in non-volatile memory | Masaaki Higashitani | 2015-02-24 |
| 8942047 | Bit line current trip point modulation for reading nonvolatile storage elements | Man Lung Mui, Teruhiko Kamei, Ken Oowada, Yosuke Kato, Fumitoshi Ito +1 more | 2015-01-27 |
| 8929141 | Three-dimensional NAND memory with adaptive erase | Deepak Raghu, Gautam Dusija, Chris Avila, Man Lung Mui, Pao-Ling Koh | 2015-01-06 |
| 8929142 | Programming select gate transistors and memory cells using dynamic verify level | Cynthia Hsu, Masaaki Higashitani, Ken Oowada | 2015-01-06 |
| 8913432 | Programming select gate transistors and memory cells using dynamic verify level | Cynthia Hsu, Masaaki Higashitani, Ken Oowada | 2014-12-16 |
| 8909493 | Compensation for sub-block erase | Chris Avila, Man Lung Mui | 2014-12-09 |
| 8902658 | Three-dimensional NAND memory with adaptive erase | Deepak Raghu, Gautam Dusija, Chris Avila, Man Lung Mui, Pao-Ling Koh | 2014-12-02 |
| 8902661 | Block structure profiling in three dimensional memory | Deepak Raghu, Gautam Dusija, Chris Avila, Man Lung Mui, Alexander Kwok-Tung Mak +1 more | 2014-12-02 |
| 8902647 | Write scheme for charge trapping memory | Deepak Raghu, Chris Avila, Gautam Dusija | 2014-12-02 |
| 8897070 | Selective word line erase in 3D non-volatile memory | Alex Mak, Seungpil Lee, Johann Alsmeier | 2014-11-25 |
| 8891308 | Dynamic erase voltage step size selection for 3D non-volatile memory | Wendy Ou, Man Lung Mui, Masaaki Higashitani | 2014-11-18 |
| 8885416 | Bit line current trip point modulation for reading nonvolatile storage elements | Man Lung Mui, Teruhiko Kamei, Ken Oowada, Yosuke Kato, Fumitoshi Ito +1 more | 2014-11-11 |
| 8873293 | Dynamic erase voltage step size selection for 3D non-volatile memory | Wendy Ou, Man Lung Mui, Masaaki Higashitani | 2014-10-28 |
| 8830717 | Optimized configurable NAND parameters | Chris Avila, Man Lung Mui | 2014-09-09 |
| 8830755 | Reducing weak-erase type read disturb in 3D non-volatile memory | Man Lung Mui, Hitoshi Miwa | 2014-09-09 |
| 8797800 | Select gate materials having different work functions in non-volatile memory | Masaaki Higashitani | 2014-08-05 |
| 8787088 | Optimized erase operation for non-volatile memory with partially programmed block | Deepanshu Dutta, Ken Oowada, Koichi Nishimura | 2014-07-22 |