PR

Peter Rabkin

ST Sandisk Technologies: 106 patents #11 of 2,224Top 1%
S3 Sandisk 3D: 11 patents #41 of 180Top 25%
SH Sk Hynix: 10 patents #756 of 4,849Top 20%
HA Hynix Semiconductor America: 4 patents #1 of 5Top 20%
AM AMD: 1 patents #5,683 of 9,279Top 65%
HA Hyundai Electronics America: 1 patents #75 of 148Top 55%
📍 Cupertino, CA: #53 of 6,989 inventorsTop 1%
🗺 California: #1,264 of 386,348 inventorsTop 1%
Overall (All Time): #7,963 of 4,157,543Top 1%
133
Patents All Time

Issued Patents All Time

Showing 51–75 of 133 patents

Patent #TitleCo-InventorsDate
11004773 Porous barrier layer for improving reliability of through-substrate via structures and methods of forming the same Chen Wu, Masaaki Higashitani 2021-05-11
10991721 Three-dimensional memory device including liner free molybdenum word lines and methods of making the same Raghuveer S. Makala, Masaaki Higashitani 2021-04-27
10978145 Programming to minimize cross-temperature threshold voltage widening Biswajit Ray, Mohan Dunga, Gerrit Jan Hemink, Changyuan Chen 2021-04-13
10923196 Erase operation in 3D NAND Kwang Ho Kim, Masaaki Higashitani 2021-02-16
10910064 Location dependent impedance mitigation in non-volatile memory Kwang Ho Kim, Masaaki Higashitani 2021-02-02
10847452 Non-volatile memory with capacitors using metal under signal line or above a device capacitor Luisa Lin, Mohan Dunga, Venkatesh Ramachandra, Masaaki Higashitani 2020-11-24
10840259 Three-dimensional memory device including liner free molybdenum word lines and methods of making the same Raghuveer S. Makala, Masaaki Higashitani 2020-11-17
10789992 Non-volatile memory with capacitors using metal under pads Luisa Lin, Mohan Dunga, Venkatesh Ramachandra, Masaaki Higashitani 2020-09-29
10763271 Three-dimensional memory device containing aluminum-silicon word lines and methods of manufacturing the same Masaaki Higashitani, Jayavel Pachamuthu 2020-09-01
10755788 Impedance mismatch mitigation scheme that applies asymmetric voltage pulses to compensate for asymmetries from applying symmetric voltage pulses Kwang Ho Kim, Masaaki Higashitani, Yingda Dong 2020-08-25
10726926 Hot-cold VTH mismatch using VREAD modulation Dae Wung Kang, Masaaki Higashitani 2020-07-28
10650898 Erase operation in 3D NAND flash memory including pathway impedance compensation Kwang Ho Kim, Masaaki Higashitani, Yingda Dong 2020-05-12
10319680 Metal contact via structure surrounded by an air gap and method of making thereof Jongsun Sel, Masaaki Higashitani, Mohan Dunga, Fumiaki Toyama 2019-06-11
10297329 NAND boosting using dynamic ramping of word line voltages Yingda Dong, Masaaki Higashitani 2019-05-21
10115459 Multiple liner interconnects for three dimensional memory devices and method of making thereof Katsuo Yamada, Tomoyasu Kakegawa, Jayavel Pachamuthu, Mohan Dunga, Masaaki Higashitani 2018-10-30
9953717 NAND structure with tier select gate transistors Jagdish Sabde, Jayavel Pachamuthu 2018-04-24
9941295 Method of making a three-dimensional memory device having a heterostructure quantum well channel Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani 2018-04-10
9881929 Multi-tier memory stack structure containing non-overlapping support pillar structures and method of making thereof Pradhyumna Ravikirthi, Jayavel Pachamuthu, Jagdish Sabde 2018-01-30
9876025 Methods for manufacturing ultrathin semiconductor channel three-dimensional memory devices Jayavel Pachamuthu, Masaaki Higashitani, Johann Alsmeier 2018-01-23
9825051 Three dimensional NAND device containing fluorine doped layer and method of making thereof Jayavel Pachamuthu, Johann Alsmeier 2017-11-21
9818801 Resistive three-dimensional memory device with heterostructure semiconductor local bit line and method of making thereof Perumal Ratnam, Christopher J. Petti, Masaaki Higashitani 2017-11-14
9799669 Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device Jayavel Pachamuthu, Johann Alsmeier 2017-10-24
9780108 Ultrathin semiconductor channel three-dimensional memory devices Jayavel Pachamuthu, Masaaki Higashitani, Johann Alsmeier 2017-10-03
9761604 3D vertical NAND with III-V channel Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani 2017-09-12
9721963 Three-dimensional memory device having a transition metal dichalcogenide channel Masaaki Higashitani 2017-08-01