Issued Patents All Time
Showing 76–100 of 133 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9711229 | 3D NAND with partial block erase | Masaaki Higashitani | 2017-07-18 |
| 9685484 | Reversible resistivity memory with crystalline silicon bit line | Perumal Ratnam, Masaaki Higashitani, Chris Petti | 2017-06-20 |
| 9685454 | Method of forming 3D vertical NAND with III-V channel | Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani | 2017-06-20 |
| 9634097 | 3D NAND with oxide semiconductor channel | Johann Alsmeier, Masaaki Higashitani | 2017-04-25 |
| 9530790 | Three-dimensional memory device containing CMOS devices over memory stack structures | Zhenyu Lu, Andrew Lin, Johann Alsmeier, Wei Zhao, Wenguang Shi +2 more | 2016-12-27 |
| 9530506 | NAND boosting using dynamic ramping of word line voltages | Yingda Dong, Masaaki Higashitani | 2016-12-27 |
| 9515085 | Vertical memory device with bit line air gap | Jilin Xia, Jayavel Pachamuthu | 2016-12-06 |
| 9478495 | Three dimensional memory device containing aluminum source contact via structure and method of making thereof | Jayavel Pachamuthu, Jilin Xia, Christopher J. Petti | 2016-10-25 |
| 9449985 | Memory cell with high-k charge trapping layer | Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani | 2016-09-20 |
| 9449980 | Band gap tailoring for a tunneling dielectric for a three-dimensional memory structure | — | 2016-09-20 |
| 9449984 | Vertical NAND device with low capacitance and silicided word lines | Johann Alsmeier | 2016-09-20 |
| 9443865 | Fabricating 3D NAND memory having monolithic crystalline silicon vertical NAND channel | Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani | 2016-09-13 |
| 9443907 | Vertical bit line wide band gap TFT decoder | Masaaki Higashitani | 2016-09-13 |
| 9425299 | Three-dimensional memory device having a heterostructure quantum well channel | Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani | 2016-08-23 |
| 9406781 | Thin film transistor | Masaaki Higashitani | 2016-08-02 |
| 9368510 | Method of forming memory cell with high-k charge trapping layer | Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani | 2016-06-14 |
| 9331093 | Three dimensional NAND device with silicon germanium heterostructure channel | Jayavel Pachamuthu | 2016-05-03 |
| 9287290 | 3D memory having crystalline silicon NAND string channel | Jayavel Pachamuthu, Johann Alsmeier, Masaaki Higashitani | 2016-03-15 |
| 9281317 | 3D non-volatile memory with metal silicide interconnect | Masaaki Higashitani | 2016-03-08 |
| 9240420 | 3D non-volatile storage with wide band gap transistor decoder | Masaaki Higashitani | 2016-01-19 |
| 9230985 | Vertical TFT with tunnel barrier | Ming-Che Wu, Tim Chen | 2016-01-05 |
| 9230980 | Single-semiconductor-layer channel in a memory opening for a three-dimensional non-volatile memory device | Jayavel Pachamuthu, Johann Alsmeier | 2016-01-05 |
| 9177966 | Three dimensional NAND devices with air gap or low-k core | Wei Zhao, Yanli Zhang, Jayavel Pachamuthu | 2015-11-03 |
| 9165933 | Vertical bit line TFT decoder for high voltage operation | Masaaki Higashitani | 2015-10-20 |
| 9129681 | Thin film transistor | Masaaki Higashitani | 2015-09-08 |