Issued Patents All Time
Showing 51–75 of 82 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9793403 | Multi-layer fin field effect transistor devices and methods of forming the same | Robert C. Bowen, Titash Rakshit, Wei-E Wang, Mark S. Rodder | 2017-10-17 |
| 9773904 | Vertical field effect transistor with biaxial stressor layer | Chris Bowen, Titash Rakshit, Palle Dharmendar, Mark S. Rodder | 2017-09-26 |
| 9741811 | Integrated circuit devices including source/drain extension regions and methods of forming the same | Ryan M. Hatcher | 2017-08-22 |
| 9716176 | FinFET semiconductor devices including recessed source-drain regions on a bottom semiconductor layer and methods of fabricating the same | Mark S. Rodder, Robert C. Bowen | 2017-07-25 |
| 9711414 | Strained stacked nanosheet FETS and/or quantum well stacked nanosheet | Ryan M. Hatcher, Robert C. Bowen, Mark S. Rodder, Joon Goo Hong | 2017-07-18 |
| 9653287 | S/D connection to individual channel layers in a nanosheet FET | Mark S. Rodder, Joon Goo Hong, Jorge A. Kittl | 2017-05-16 |
| 9647098 | Thermionically-overdriven tunnel FETs and methods of fabricating the same | Robert C. Bowen, Dharmendar Reddy Palle, Mark S. Rodder | 2017-05-09 |
| 9614002 | 0T bi-directional memory cell | Ryan M. Hatcher, Titash Rakshit, Jorge A. Kittl, Joon Goo Hong | 2017-04-04 |
| 9583590 | Integrated circuit devices including FinFETs and methods of forming the same | Robert C. Bowen, Mark S. Rodder | 2017-02-28 |
| 9570609 | Crystalline multiple-nanosheet strained channel FETs and methods of fabricating the same | Robert C. Bowen, Mark S. Rodder | 2017-02-14 |
| 9490323 | Nanosheet FETs with stacked nanosheets having smaller horizontal spacing than vertical spacing for large effective width | Mark S. Rodder, Rwik Sengupta | 2016-11-08 |
| 9484423 | Crystalline multiple-nanosheet III-V channel FETs | Jorge A. Kittl, Mark. S. Rodder | 2016-11-01 |
| 9466669 | Multiple channel length finFETs with same physical gate length | Mark S. Rodder, Rwik Sengupta | 2016-10-11 |
| 9461114 | Semiconductor devices with structures for suppression of parasitic bipolar effect in stacked nanosheet FETs and methods of fabricating the same | Ryan M. Hatcher, Robert C. Bowen, Mark S. Rodder | 2016-10-04 |
| 9425275 | Integrated circuit chips having field effect transistors with different gate designs | Mark S. Rodder, Dharmendar Reddy Palle | 2016-08-23 |
| 9287357 | Integrated circuits with Si and non-Si nanosheet FET co-integration with low band-to-band tunneling and methods of fabricating the same | Mark S. Rodder, Rwik Sengupta, Dharmendar Reddy Palle, Robert C. Bowen | 2016-03-15 |
| 9178045 | Integrated circuit devices including FinFETS and methods of forming the same | Robert C. Bowen, Mark S. Rodder | 2015-11-03 |
| 9112130 | Quantum interference based logic devices including electron monochromator | Robert C. Bowen | 2015-08-18 |
| 9013167 | Hall effect device having voltage based biasing for temperature compensation | Anthony G. Antonacci, Keith Ryan Green | 2015-04-21 |
| 8380476 | Modeling of ferroelectric capacitors to include local statistical variations of ferroelectric properties | Keith Ryan Green, Scott R. Summerfelt | 2013-02-19 |
| 8170858 | Characterization and modeling of ferroelectric capacitors | Keith Ryan Green | 2012-05-01 |
| 8119470 | Mitigation of gate to contact capacitance in CMOS flow | Shashank S. Ekbote, Lindsey Hall, Craig Huffman, Ajith Varghese | 2012-02-21 |
| 8114729 | Differential poly doping and circuits therefrom | Shashank S. Ekbote, Kamel Benaissa, Greg Baldwin | 2012-02-14 |
| 7892930 | Method to improve transistor tox using SI recessing with no additional masking steps | Shashank S. Ekbote | 2011-02-22 |
| 7812401 | MOS device and process having low resistance silicide interface using additional source/drain implant | Shashank S. Ekbote, Mark Visokay | 2010-10-12 |