Issued Patents All Time
Showing 501–525 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9111645 | Request-command encoding for reduced-data-rate testing | Kishore Ven Kasamsetty, Wayne S. Richardson, Kurt Knorpp | 2015-08-18 |
| 9111587 | Stacked memory with redundancy | Paul D. Franzon | 2015-08-18 |
| 9110596 | Fast-wake memory | Jared L. Zerbe, Brian S. Leibowitz | 2015-08-18 |
| 9099194 | Memory component with pattern register circuitry to provide data patterns for calibration | Craig E. Hampel, Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern | 2015-08-04 |
| 9092352 | Memory controller with write data error detection and remediation | Yuanlong Wang | 2015-07-28 |
| 9087568 | Memory with merged control input | — | 2015-07-21 |
| 9053778 | Memory controller that enforces strobe-to-strobe timing offset | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2015-06-09 |
| 9043633 | Memory controller with transaction-queue-monitoring power mode circuitry | Robert E. Palmer, John W. Poulton, Andrew M. Fuller | 2015-05-26 |
| 9042504 | Communication channel calibration for drift conditions | Richard E. Perego, Craig E. Hampel | 2015-05-26 |
| 9037949 | Error correction in a memory device | Thomas Vogelsang, Suresh Rajan, Ian Shaeffer, Wayne F. Ellis | 2015-05-19 |
| 9007853 | Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift | — | 2015-04-14 |
| 9009400 | Semiconductor memory systems with on-die data buffering | Amir Amirkhany, Suresh Rajan, Mohammad Hekmat, Dinesh Patil | 2015-04-14 |
| 9007862 | Reducing memory refresh exit time | Brent Haukness, Ian Shaeffer, James E. Harris | 2015-04-14 |
| 8982598 | Stacked memory device with redundant resources to correct defects | Paul D. Franzon, Evan Lawrence Erickson, Thomas Vogelsang | 2015-03-17 |
| 8949520 | Maintenance operations in a DRAM | Robert E. Palmer, John W. Poulton | 2015-02-03 |
| 8942056 | Protocol for memory power-mode control | Wayne F. Ellis, Wayne S. Richardson, Akash Bansal, Lawrence Lai, Kishore Ven Kasamsetty | 2015-01-27 |
| 8943224 | Chip selection in a symmetric interconnection topology | Brian S. Leibowitz | 2015-01-27 |
| 8942309 | Signal output improvement using data inversion and/or swapping | John Wilson | 2015-01-27 |
| 8930779 | Bit-replacement technique for DRAM error correction | Ely Tsern, Thomas Vogelsang | 2015-01-06 |
| 8929424 | Periodic calibration for communication channels by drift tracking | Craig E. Hampel, Richard E. Perego | 2015-01-06 |
| 8924680 | Memory controllers, systems, and methods supporting multiple request modes | Richard E. Perego | 2014-12-30 |
| 8918703 | Memory system with error detection and retry modes of operation | Ely Tsern, Mark A. Horowitz | 2014-12-23 |
| 8918667 | Mesochronous signaling system with core-clock synchronization | Robert E. Palmer, John W. Poulton, Andrew M. Fuller | 2014-12-23 |
| 8918669 | Mesochronous signaling system with clock-stopped low power mode | Robert E. Palmer, John W. Poulton, Andrew M. Fuller | 2014-12-23 |
| 8908466 | Multi-column addressing mode memory system including an integrated circuit memory device | Lawrence Lai, Chad A. Bellows, Wayne S. Richardson | 2014-12-09 |