Issued Patents All Time
Showing 551–575 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8593885 | Staggered mode transitions in a segmented interface | — | 2013-11-26 |
| 8588280 | Asymmetric communication on shared links | Kyung Suk Oh, John Wilson, WooPoung KIM, Jade M. Kizer, Brian S. Leibowitz +2 more | 2013-11-19 |
| 8581920 | Utilizing masked data bits during accesses to a memory | Lei Luo, John Wilson, Jade M. Kizer | 2013-11-12 |
| 8560797 | Method and apparatus for indicating mask information | Richard M. Barth, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2013-10-15 |
| 8553475 | Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift | — | 2013-10-08 |
| 8537601 | Memory controller with selective data transmission delay | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2013-09-17 |
| 8510495 | Cross-threaded memory system | Kishore Ven Kasamsetty | 2013-08-13 |
| 8504790 | Memory component having write operation with multiple time periods | Paul G. Davis, Craig E. Hampel | 2013-08-06 |
| 8504788 | Memory controller, system and method for read signal timing calibration | Bret G. Stott, Ian Shaeffer, Yuanlong Wang | 2013-08-06 |
| 8497544 | Repairing defects in a nonvolatile semiconductor memory module utilizing a heating element | Gary B. Bronner, Ming Li, Donald R. Mullen, Kevin S. Donnelly | 2013-07-30 |
| 8493802 | Memory controller having a write-timing calibration mode | — | 2013-07-23 |
| 8462891 | Error detection and offset cancellation during multi-wire communication | Jade M. Kizer, John Wilson, Lei Luo, Jared L. Zerbe | 2013-06-11 |
| 8462566 | Memory module with termination component | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2013-06-11 |
| 8451674 | Clock synchronization in a memory system | Jade M. Kizer, John M. Wilson, John Eble | 2013-05-28 |
| 8441872 | Memory controller with adjustable width strobe interface | Jade M. Kizer, Yoshihito Koya | 2013-05-14 |
| 8432766 | Multi-column addressing mode memory system including an integrated circuit memory device | Lawrence Lai, Chad A. Bellows, Wayne S. Richardson | 2013-04-30 |
| 8432768 | Mesochronous signaling system with multiple power modes | Robert E. Palmer, John W. Poulton | 2013-04-30 |
| 8422568 | Communication channel calibration for drift conditions | Richard E. Perego, Craig E. Hampel | 2013-04-16 |
| 8412906 | Memory apparatus supporting multiple width configurations | Richard E. Perego, Donald C. Stark, Ely Tsern, Craig E. Hampel | 2013-04-02 |
| 8395951 | Memory controller | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2013-03-12 |
| 8391039 | Memory module with termination component | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2013-03-05 |
| 8380927 | Upgradable system with reconfigurable interconnect | Richard E. Perego, Ely Tsern, Craig E. Hampel | 2013-02-19 |
| 8369164 | Bimodal memory controller | — | 2013-02-05 |
| 8363493 | Memory controller having a write-timing calibration mode | — | 2013-01-29 |
| 8365042 | Unidirectional error code transfer for both read and write data transmitted via bidirectional data link | Yuanlong Wang | 2013-01-29 |