Issued Patents All Time
Showing 576–600 of 739 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8364926 | Memory module with reduced access granularity | Craig E. Hampel | 2013-01-29 |
| 8359445 | Method and apparatus for signaling between devices of a memory system | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2013-01-22 |
| 8351281 | Early read after write operation memory device, system and method | Richard E. Perego | 2013-01-08 |
| 8347047 | Memory system and device with serialized data transfer | Richard E. Perego | 2013-01-01 |
| 8344475 | Integrated circuit heating to effect in-situ annealing | Ian Shaeffer, Gary B. Bronner, Brent Haukness, Kevin S. Donnelly, Mark A. Horowitz | 2013-01-01 |
| 8339895 | Signal calibration methods and apparatuses | Reza Navid, John W. Poulton | 2012-12-25 |
| 8320202 | Clocked memory system with termination component | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2012-11-27 |
| 8310872 | Multi-page parallel program flash memory | Yoshihito Koya, Gary B. Bronner | 2012-11-13 |
| 8305821 | Memory systems and methods for dynamically phase adjusting a write strobe and data to account for receive-clock drift | — | 2012-11-06 |
| 8295107 | Asynchronous pipelined memory access | Ely Tsern, Craig E. Hampel, Donald C. Stark | 2012-10-23 |
| 8278964 | Method and apparatus for test and characterization of semiconductor components | Scott C. Best, Timothy Chang, Richard Perego, Ely Tsern, Jeff Mitchell | 2012-10-02 |
| 8271745 | Memory controller for non-homogeneous memory system | — | 2012-09-18 |
| 8260979 | Method and apparatus for simultaneous bidirectional signaling in a bus topology | — | 2012-09-04 |
| 8261039 | Memory controllers, methods, and systems supporting multiple memory modes | Richard E. Perego | 2012-09-04 |
| 8255734 | Multi-drop signaling system and method employing source termination | Bret G. Stott | 2012-08-28 |
| 8243484 | Adjustable width strobe interface | Jade M. Kizer, Yoshihito Koya | 2012-08-14 |
| 8218382 | Memory component having a write-timing calibration mode | — | 2012-07-10 |
| 8214616 | Memory controller device having timing offset capability | Ely Tsern, Richard E. Perego, Craig E. Hampel | 2012-07-03 |
| 8208593 | Partial-rate transfer mode for fixed-clock-rate interface | Robert E. Palmer, John W. Poulton | 2012-06-26 |
| 8205056 | Memory controller for controlling write signaling | Richard M. Barth, Donald C. Stark, Craig E. Hampel, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2012-06-19 |
| 8195907 | Timing adjustment in a reconfigurable system | Ian Shaeffer, Scott C. Best, Craig E. Hampel | 2012-06-05 |
| 8193573 | Repairing defects in a nonvolatile semiconductor memory device utilizing a heating element | Gary B. Bronner, Ming Li, Donald R. Mullen, Kevin S. Donnelly | 2012-06-05 |
| 8194493 | Low power memory device | Ely Tsern, Craig E. Hampel | 2012-06-05 |
| 8174923 | Voltage-stepped low-power memory device | Yoshihito Koya | 2012-05-08 |
| 8165187 | Periodic calibration for communication channels by drift tracking | Craig E. Hampel, Richard E. Perego | 2012-04-24 |