Issued Patents All Time
Showing 101–125 of 310 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9117035 | Memory system topologies including a buffer device and an integrated circuit memory device | Ian Shaeffer, Ely Tsern | 2015-08-25 |
| 9110828 | Chip having register to store value that represents adjustment to reference voltage | Mark A. Horowitz, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe | 2015-08-18 |
| 9099194 | Memory component with pattern register circuitry to provide data patterns for calibration | Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern, Frederick A. Ware | 2015-08-04 |
| 9053778 | Memory controller that enforces strobe-to-strobe timing offset | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2015-06-09 |
| 9042504 | Communication channel calibration for drift conditions | Frederick A. Ware, Richard E. Perego | 2015-05-26 |
| 8929424 | Periodic calibration for communication channels by drift tracking | Frederick A. Ware, Richard E. Perego | 2015-01-06 |
| 8868873 | Reconfigurable memory system data strobes | Ian Shaeffer, Frederick A. Ware | 2014-10-21 |
| 8838900 | Atomic-operation coalescing technique in multi-chip systems | Qi Lin, Liang Ping Peng, Thomas J. Sheffler, Steven C. Woo, Bohuslav Rychlik | 2014-09-16 |
| 8811095 | Methods and circuits for dynamically scaling DRAM power and performance | Ely Tsern, Thomas Vogelsang, Scott C. Best | 2014-08-19 |
| 8775705 | Chip having register to store value that represents adjustment to reference voltage | Mark A. Horowitz, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe | 2014-07-08 |
| 8769234 | Memory modules and devices supporting configurable data widths | Richard E. Perego, Donald C. Stark, Frederick A. Ware, Ely Tsern | 2014-07-01 |
| 8760944 | Memory component that samples command/address signals in response to both edges of a clock signal | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2014-06-24 |
| 8762657 | Method and system for synchronizing address and control signals in threaded memory modules | Arun Vaidyanath | 2014-06-24 |
| 8756395 | Controlling DRAM at time DRAM ready to receive command when exiting power down | Richard M. Barth, Ely Tsern, Frederick A. Ware, Todd Bystrom, Bradley A. May +1 more | 2014-06-17 |
| 8717837 | Memory module | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2014-05-06 |
| 8707110 | Memory error detection | Ian Shaeffer | 2014-04-22 |
| 8693556 | Communication channel calibration for drift conditions | Frederick A. Ware, Richard E. Perego | 2014-04-08 |
| 8644419 | Periodic calibration for communication channels by drift tracking | Frederick A. Ware, Richard E. Perego | 2014-02-04 |
| 8625371 | Memory component with terminated and unterminated signaling inputs | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2014-01-07 |
| 8595459 | Micro-threaded memory | Frederick A. Ware, Wayne S. Richardson, Chad A. Bellows, Lawrence Lai | 2013-11-26 |
| 8560797 | Method and apparatus for indicating mask information | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2013-10-15 |
| 8555116 | Memory error detection | Ian Shaeffer | 2013-10-08 |
| 8542787 | Phase adjustment apparatus and method for a memory device signaling system | Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern, Fredrick A. Ware | 2013-09-24 |
| 8537601 | Memory controller with selective data transmission delay | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2013-09-17 |
| 8539152 | Memory system topologies including a buffer device and an integrated circuit memory device | Ian Shaeffer, Ely Tsern | 2013-09-17 |