Issued Patents All Time
Showing 151–175 of 310 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8144792 | Communication channel calibration for drift conditions | Frederick A. Ware, Richard E. Perego | 2012-03-27 |
| 8140805 | Memory component having write operation with multiple time periods | Paul G. Davis, Frederick A. Ware | 2012-03-20 |
| 8127152 | Method of operation of a memory device and system including initialization at a first frequency and operation at a second frequency and a power down exit mode | Richard M. Barth, Ely Tsern, Frederick A. Ware, Todd Bystrom, Bradley A. May +1 more | 2012-02-28 |
| 8121237 | Signaling system with adaptive timing calibration | Bret G. Stott, Frederick A. Ware | 2012-02-21 |
| 8112608 | Variable-width memory | Richard E. Perego, Donald C. Stark, Frederick A. Ware, Ely Tsern | 2012-02-07 |
| 8108607 | Memory system topologies including a buffer device and an integrated circuit memory device | Ian Shaeffer, Ely Tsern | 2012-01-31 |
| 8059476 | Control component for controlling a delay interval within a memory component | Frederick A. Ware, Ely Tsern, Donald C. Stark | 2011-11-15 |
| 8060665 | Integrated circuit input/output interface with empirically determined delay matching | Scott C. Best | 2011-11-15 |
| 8028144 | Memory module with reduced access granularity | Frederick A. Ware | 2011-09-27 |
| 8019958 | Memory write signaling and methods thereof | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2011-09-13 |
| 8018789 | Methods and systems for reducing heat flux in memory systems | Steven C. Woo | 2011-09-13 |
| 8001305 | System and dynamic random access memory device having a receiver | Mark A. Horowitz, Richard M. Barth, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe | 2011-08-16 |
| 7986584 | Memory device having multiple power modes | Ely Tsern, Richard M. Barth, Donald C. Stark | 2011-07-26 |
| 7965567 | Phase adjustment apparatus and method for a memory device signaling system | Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern, Fredrick A. Ware | 2011-06-21 |
| 7916570 | Low power memory device | Frederick A. Ware, Ely Tsern | 2011-03-29 |
| 7870357 | Memory system and method for two step memory write operations | Paul G. Davis, Frederick A. Ware | 2011-01-11 |
| 7836378 | System to detect and identify errors in control information, read data and/or write data | Ian Shaeffer, Yuanlong Wang, Fred Ware | 2010-11-16 |
| 7830735 | Asynchronous, high-bandwidth memory component using calibrated timing elements | Frederick A. Ware, Ely Tsern, Donald C. Stark | 2010-11-09 |
| 7793039 | Interface for a semiconductor memory device and method for controlling the interface | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2010-09-07 |
| 7729151 | System including a buffered memory module | Ely Tsern, Ian Shaeffer | 2010-06-01 |
| 7685364 | Memory system topologies including a buffer device and an integrated circuit memory device | Ian Shaeffer, Ely Tsern | 2010-03-23 |
| 7668276 | Phase adjustment apparatus and method for a memory device signaling system | Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern, Fredrick A. Ware | 2010-02-23 |
| 7660183 | Low power memory device | Frederick A. Ware, Ely Tsern | 2010-02-09 |
| 7626880 | Memory device having a read pipeline and a delay locked loop | Ely Tsern, Richard M. Barth, Donald C. Stark | 2009-12-01 |
| 7613883 | Memory device with mode-selectable prefetch and clock-to-core timing | Chad A. Bellows | 2009-11-03 |