Issued Patents All Time
Showing 201–225 of 310 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7349279 | Memory Device Having a Configurable Oscillator for Refresh Operation | Ely Tsern, Richard M. Barth, Paul G. Davis | 2008-03-25 |
| 7330953 | Memory system having delayed write timing | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2008-02-12 |
| 7330952 | Integrated circuit memory device having delayed write timing based on read response time | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2008-02-12 |
| 7330951 | Apparatus and method for pipelined memory operations | John B. Dillon, Ely Tsern, Mark A. Horowitz, Donald C. Stark, Frederick A. Ware +1 more | 2008-02-12 |
| 7320082 | Power control system for synchronous memory device | Ely Tsern, Richard M. Barth, Donald C. Stark | 2008-01-15 |
| 7315929 | Memory device | Richard M. Barth, Mark A. Horowitz, Frederick A. Ware | 2008-01-01 |
| 7287109 | Method of controlling a memory device having a memory core | Richard M. Barth, Frederick A. Ware, John B. Dillon, Donald C. Stark, Matthew Murdy Griffin | 2007-10-23 |
| 7287119 | Integrated circuit memory device with delayed write command processing | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2007-10-23 |
| 7225311 | Method and apparatus for coordinating memory operations among diversely-located memory components | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2007-05-29 |
| 7225292 | Memory module with termination component | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2007-05-29 |
| 7222209 | Expandable slave device system | Bruno W. Garlepp, Richard M. Barth, Kevin S. Donnelly, Ely Tsern, Jeffrey D. Mitchell +4 more | 2007-05-22 |
| 7213121 | Memory device having asynchronous/synchronous operating modes | Richard M. Barth, Mark A. Horowitz, Frederick A. Ware | 2007-05-01 |
| 7210016 | Method, system and memory controller utilizing adjustable write data delay settings | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2007-04-24 |
| 7210015 | Memory device having at least a first and a second operating mode | Richard M. Barth, Mark A. Horowitz, Frederick A. Ware | 2007-04-24 |
| 7209397 | Memory device with clock multiplier circuit | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2007-04-24 |
| 7200055 | Memory module with termination component | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2007-04-03 |
| 7197611 | Integrated circuit memory device having write latency function | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2007-03-27 |
| 7177998 | Method, system and memory controller utilizing adjustable read data delay settings | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2007-02-13 |
| 7174400 | Integrated circuit device that stores a value representative of an equalization co-efficient setting | Mark A. Horowitz, Richard M. Barth, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe | 2007-02-06 |
| 7142475 | Memory device having a configurable oscillator for refresh operation | Ely Tsern, Richard M. Barth, Paul G. Davis | 2006-11-28 |
| 7136949 | Method and apparatus for position dependent data scheduling | — | 2006-11-14 |
| 7095789 | Communication channel calibration for drift conditions | Frederick A. Ware, Richard E. Perego | 2006-08-22 |
| 7085906 | Memory device | Richard M. Barth, Mark A. Horowitz, Frederick A. Ware | 2006-08-01 |
| 7073035 | Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules | Frederick A. Ware, Richard E. Perego, Ely Tsern | 2006-07-04 |
| 7051129 | Memory device having programmable drive strength setting | Mark A. Horowitz, Richard M. Barth, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe | 2006-05-23 |