Issued Patents All Time
Showing 126–150 of 310 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8504790 | Memory component having write operation with multiple time periods | Paul G. Davis, Frederick A. Ware | 2013-08-06 |
| 8473681 | Atomic-operation coalescing technique in multi-chip systems | Qi Lin, Liang Ping Peng, Thomas J. Sheffler, Steven C. Woo, Bohuslav Rychlik | 2013-06-25 |
| 8462566 | Memory module with termination component | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2013-06-11 |
| 8458385 | Chip having register to store value that represents adjustment to reference voltage | Mark A. Horowitz, Richard M. Barth, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe | 2013-06-04 |
| 8422568 | Communication channel calibration for drift conditions | Frederick A. Ware, Richard E. Perego | 2013-04-16 |
| 8412906 | Memory apparatus supporting multiple width configurations | Richard E. Perego, Donald C. Stark, Frederick A. Ware, Ely Tsern | 2013-04-02 |
| 8395951 | Memory controller | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2013-03-12 |
| 8391039 | Memory module with termination component | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2013-03-05 |
| 8380927 | Upgradable system with reconfigurable interconnect | Richard E. Perego, Frederick A. Ware, Ely Tsern | 2013-02-19 |
| 8364926 | Memory module with reduced access granularity | Frederick A. Ware | 2013-01-29 |
| 8359445 | Method and apparatus for signaling between devices of a memory system | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2013-01-22 |
| 8356127 | Memory interface with workload adaptive encode/decode | — | 2013-01-15 |
| 8352805 | Memory error detection | Ian Shaeffer | 2013-01-08 |
| 8352696 | Integrated circuit with bi-modal data strobe | — | 2013-01-08 |
| 8320202 | Clocked memory system with termination component | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2012-11-27 |
| 8305839 | Memory device having multiple power modes | Ely Tsern, Richard M. Barth, Donald C. Stark | 2012-11-06 |
| 8295107 | Asynchronous pipelined memory access | Frederick A. Ware, Ely Tsern, Donald C. Stark | 2012-10-23 |
| 8248884 | Method of controlling a memory device having multiple power modes | Ely Tsern, Richard M. Barth, Donald C. Stark | 2012-08-21 |
| 8214616 | Memory controller device having timing offset capability | Frederick A. Ware, Ely Tsern, Richard E. Perego | 2012-07-03 |
| 8214570 | Memory controller and method utilizing equalization co-efficient setting | Mark A. Horowitz, Richard M. Barth, Alfredo Moncayo, Kevin S. Donnelly, Jared L. Zerbe | 2012-07-03 |
| 8205056 | Memory controller for controlling write signaling | Richard M. Barth, Frederick A. Ware, Donald C. Stark, Paul G. Davis, Abhijit M. Abhyankar +2 more | 2012-06-19 |
| 8195907 | Timing adjustment in a reconfigurable system | Frederick A. Ware, Ian Shaeffer, Scott C. Best | 2012-06-05 |
| 8194493 | Low power memory device | Frederick A. Ware, Ely Tsern | 2012-06-05 |
| 8184497 | Methods and systems for reducing heat flux in memory systems | Steven C. Woo | 2012-05-22 |
| 8165187 | Periodic calibration for communication channels by drift tracking | Frederick A. Ware, Richard E. Perego | 2012-04-24 |