Issued Patents All Time
Showing 101–125 of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9465961 | Methods and circuits for securing proprietary memory transactions | Frederick A. Ware, Pradeep Batra, Trung Diep | 2016-10-11 |
| 9453879 | On-die system for monitoring and predicting performance | Mohamed H. Abu-Rahma, Michael R. Seningen | 2016-09-27 |
| 9455825 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2016-09-27 |
| 9423441 | Integrated circuit having receiver jitter tolerance (“JTOL”) measurement | Hae-Chang Lee, Jaeha Kim | 2016-08-23 |
| 9425997 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Hae-Chang Lee, Jihong Ren, Qi Lin | 2016-08-23 |
| 9419663 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Hae-Chang Lee, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2016-08-16 |
| 9419781 | Receiver with enhanced clock and data recovery | Hae-Chang Lee, Jaeha Kim, Jafar Savoj | 2016-08-16 |
| 9391816 | Edge based partial response equalization | Hae-Chang Lee, Jihong Ren, Ruwan Ratnayake | 2016-07-12 |
| 9344074 | Low-latency, frequency-agile clock multiplier | Jared L. Zerbe, Masum Hossain | 2016-05-17 |
| 9337992 | Clock and data recovery using receiver clock spread spectrum modulation and offset compensation | Hae-Chang Lee, Thomas Hastings Greer, III, Jade M. Kizer, Mark A. Horowitz | 2016-05-10 |
| 9304579 | Fast-wake memory control | Frederick A. Ware, Jared L. Zerbe | 2016-04-05 |
| 9287880 | Integrated circuit device having an injection-locked oscillator | Marko Aleksic | 2016-03-15 |
| 9264055 | Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator | Marko Aleksic | 2016-02-16 |
| 9262342 | Process authenticated memory page encryption | Trung Diep, Pradeep Batra, Frederick A. Ware | 2016-02-16 |
| 9215112 | Decision feedback equalizer | Jaeha Kim | 2015-12-15 |
| 9178688 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2015-11-03 |
| 9178647 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Simon Li, Nhat Nguyen | 2015-11-03 |
| 9148322 | High-speed signaling systems with adaptable pre-emphasis and equalization | Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton +1 more | 2015-09-29 |
| 9137063 | High-speed signaling systems with adaptable pre-emphasis and equalization | Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton +1 more | 2015-09-15 |
| 9117496 | Memory device comprising programmable command-and-address and/or data interfaces | Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson +2 more | 2015-08-25 |
| 9110596 | Fast-wake memory | Frederick A. Ware, Jared L. Zerbe | 2015-08-18 |
| 9094238 | High-speed signaling systems with adaptable pre-emphasis and equalization | Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton +1 more | 2015-07-28 |
| 9083280 | Techniques for phase detection | Hae-Chang Lee, Farshid Aryanfar, Kun-Yung Chang, Jie Shen | 2015-07-14 |
| 9077575 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Hae-Chang Lee, Jihong Ren, Qi Lin | 2015-07-07 |
| 9046909 | On-chip regulator with variable load compensation | Michael D. Bucher, Lei Luo, Chaofeng Huang, Amir Amirkhany, Huy M. Nguyen +2 more | 2015-06-02 |