Issued Patents All Time
Showing 126–150 of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8989249 | High-speed signaling systems with adaptable pre-emphasis and equalization | Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton +1 more | 2015-03-24 |
| 8964879 | Crosstalk reduction coding schemes | Reza Navid, Amir Amirkhany, Dinesh Patil | 2015-02-24 |
| 8943224 | Chip selection in a symmetric interconnection topology | Frederick A. Ware | 2015-01-27 |
| 8941420 | Low-latency, frequency-agile clock multiplier | Jared L. Zerbe, Masum Hossain | 2015-01-27 |
| 8934525 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Hae-Chang Lee, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2015-01-13 |
| 8929496 | Receiver with enhanced clock and data recovery | Hae-Chang Lee, Jaeha Kim, Jafar Savoj | 2015-01-06 |
| 8923467 | Clock and data recovery using receiver clock spread spectrum modulation and offset compensation | Hae-Chang Lee, Thomas Hastings Greer, III, Jade M. Kizer, Mark A. Horowitz | 2014-12-30 |
| 8855217 | Interface with variable data rate | Yohan U. Frans, Hae-Chang Lee, Simon Li, Nhat Nguyen | 2014-10-07 |
| 8836394 | Method and apparatus for source-synchronous signaling | Jared L. Zerbe, Hsuan-Jung Su, John Eble, Barry William Daly, Lei Luo +4 more | 2014-09-16 |
| 8824224 | Frequency-agile strobe window generation | Frederick A. Ware, Ely Tsern | 2014-09-02 |
| 8824222 | Fast-wake memory | Frederick A. Ware, Jared L. Zerbe | 2014-09-02 |
| 8811553 | Edge based partial response equalization | Hae-Chang Lee, Jihong Ren, Ruwan Ratnayake | 2014-08-19 |
| 8804397 | Integrated circuit having a clock deskew circuit that includes an injection-locked oscillator | Marko Aleksic | 2014-08-12 |
| 8766647 | Method and apparatus for power sequence timing to mitigate supply resonance in power distribution network | Haechang Lee | 2014-07-01 |
| 8743973 | Receiver resistor network for common-mode signaling | Lei Luo, Jared L. Zerbe, Barry William Daly, Wayne D. Dettloff, John Eble +1 more | 2014-06-03 |
| 8667347 | Active calibration for high-speed memory devices | Jared L. Zerbe, Frederick A. Ware | 2014-03-04 |
| 8618869 | Fast power-on bias circuit | Wayne D. Dettloff, John Wilson, Lei Luo, Jared L. Zerbe, Pravin Kumar Venkatesan | 2013-12-31 |
| 8588280 | Asymmetric communication on shared links | Kyung Suk Oh, John Wilson, Frederick A. Ware, WooPoung KIM, Jade M. Kizer +2 more | 2013-11-19 |
| 8548110 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2013-10-01 |
| 8477834 | Partial response decision-feedback equalization with adaptation based on edge samples | Hae-Chang Lee, Jihong Ren, Ruwan Ratnayake | 2013-07-02 |
| 8477835 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Hae-Chang Lee, Jihong Ren, Qi Lin | 2013-07-02 |
| 8422590 | Apparatus and methods for differential signal receiving | Jaeha Kim, Hae-Chang Lee | 2013-04-16 |
| 8311176 | Clock and data recovery employing piece-wise estimation on the derivative of the frequency | Hae-Chang Lee, Thomas Hastings Greer, III, Jade M. Kizer, Mark A. Horowitz | 2012-11-13 |
| 8289032 | Integrated circuit having receiver jitter tolerance (“JTOL”) measurement | Hae-Chang Lee, Jaeha Kim | 2012-10-16 |
| 8279976 | Signaling with superimposed differential-mode and common-mode signals | Qi Lin, Hae-Chang Lee, Jaeha Kim, Jared L. Zerbe, Jihong Ren | 2012-10-02 |