Issued Patents All Time
Showing 26–50 of 155 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11184012 | Detecting power supply noise events and initiating corrective action | Jared L. Zerbe, Sanjay Pant | 2021-11-23 |
| 11165613 | High-speed signaling systems with adaptable pre-emphasis and equalization | Jared L. Zerbe, Fred F. Chen, Andrew Ho, Ramin Farjad-Rad, John W. Poulton +2 more | 2021-11-02 |
| 11115247 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Hae-Chang Lee, Jihong Ren, Qi Lin | 2021-09-07 |
| 11063791 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2021-07-13 |
| 11023403 | Chip to chip interface with scalable bandwidth | Jafar Savoj, Jose A. Tierno, Sanjeev K. Maheshwari, Pradeep Trivedi, Gin Yee +1 more | 2021-06-01 |
| 11022639 | Integrated circuit that injects offsets into recovered clock to simulate presence of jitter in input signal | Hae-Chang Lee, Jaeha Kim | 2021-06-01 |
| 10951218 | Multi-mode clock multiplier | Jared L. Zerbe, Masum Hossain | 2021-03-16 |
| 10938605 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Hae-Chang Lee, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2021-03-02 |
| 10924124 | Downshift techniques for oscillator with feedback loop | Jared L. Zerbe, Sanjay Pant | 2021-02-16 |
| 10887076 | Receiver with enhanced clock and data recovery | Hae-Chang Lee, Jaeha Kim, Jafar Savoj | 2021-01-05 |
| 10880128 | Decision feedback equalizer | Jaeha Kim | 2020-12-29 |
| 10855496 | Edge based partial response equalization | Hae-Chang Lee, Jihong Ren, Ruwan Ratnayake | 2020-12-01 |
| 10840920 | Method and apparatus for source-synchronous signaling | Jared L. Zerbe, Hsuan-Jung Su, John Eble, Barry William Daly, Lei Luo +4 more | 2020-11-17 |
| 10770124 | Memory device comprising programmable command-and-address and/or data interfaces | Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson +2 more | 2020-09-08 |
| 10764093 | DFE margin test methods and circuits that decouple sample feedback timing | Bruno W. Garlepp | 2020-09-01 |
| 10756849 | Self referenced single-ended chip to chip communication | Jafar Savoj, Praveen R. Singh, Emerson S. Fang | 2020-08-25 |
| 10700671 | Data transmission using delayed timing signals | Frederick A. Ware, Ely Tsern, Jared L. Zerbe | 2020-06-30 |
| 10686632 | Methods and circuits for asymmetric distribution of channel equalization between devices | Jared L. Zerbe, Fariborz Assaderaghi, Hae-Chang Lee, Jihong Ren, Qi Lin | 2020-06-16 |
| 10650872 | Memory component with multiple command/address sampling modes | Frederick A. Ware, Ely Tsern, Wayne F. Ellis, Akash Bansal, John Brooks +1 more | 2020-05-12 |
| 10630300 | Downshift techniques for oscillator with feedback loop | Jared L. Zerbe, Sanjay Pant | 2020-04-21 |
| 10608652 | Frequency-agile clock multiplier | Jared L. Zerbe, Masum Hossain | 2020-03-31 |
| 10581440 | Detecting power supply noise events and initiating corrective action | Jared L. Zerbe, Sanjay Pant | 2020-03-03 |
| 10560291 | High-speed signaling systems and methods with adaptable, continuous-time equalization | Hae-Chang Lee, Jade M. Kizer, Thomas Hastings Greer, III, Akash Bansal | 2020-02-11 |
| 10541693 | Method and apparatus for source-synchronous signaling | Jared L. Zerbe, Hsuan-Jung Su, John Eble, Barry William Daly, Lei Luo +4 more | 2020-01-21 |
| 10536304 | Receiver with clock recovery circuit and adaptive sample and equalizer timing | Qi Lin, Hae-Chang Lee, Jihong Ren, Kyung Suk Oh, Jared L. Zerbe | 2020-01-14 |