Issued Patents All Time
Showing 26–50 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9710269 | Early conditional selection of an operand | James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2017-07-18 |
| 9514061 | Method and apparatus for cache tag compression | Henry A. Pellerin, Thomas Philip Speier, Thomas Andrew Sartorius, Michael William Morrow, James Norris Dieffenderfer +1 more | 2016-12-06 |
| 9477476 | Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Brian Michael Stempel, Rodney Wayne Smith +2 more | 2016-10-25 |
| 9477478 | Multi level indirect predictor using confidence counter and program counter address filter scheme | Kulin N. Kothari, Michael William Morrow, James Norris Dieffenderfer, Brian Michael Stempel, Daren Eugene Streett | 2016-10-25 |
| 9471325 | Method and apparatus for selective renaming in a microprocessor | Anil Krishna, Sandeep Suresh Navada, Niket K. Choudhary, Thomas Andrew Sartorius, Rodney Wayne Smith +1 more | 2016-10-18 |
| 9460018 | Method and apparatus for tracking extra data permissions in an instruction cache | Leslie Mark DeBruyne, James Norris Dieffenderfer, Brian Michael Stempel | 2016-10-04 |
| 9411590 | Method to improve speed of executing return branch instructions in a processor | Rodney Wayne Smith, Jeffery M. Schottmiller, Brian Michael Stempel, Melinda J. Brown, Daren Eugene Streett | 2016-08-09 |
| 9317293 | Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce execution pipeline bubbles, and related systems, methods, and computer-readable media | James Norris Dieffenderfer, Michael William Morrow, Daren Eugene Streett, Vimal Reddy, Brian Michael Stempel | 2016-04-19 |
| 9195466 | Fusing conditional write instructions having opposite conditions in instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, James Norris Dieffenderfer, Brian Michael Stempel, Rodney Wayne Smith, Jeffery M. Schottmiller +2 more | 2015-11-24 |
| 9146741 | Eliminating redundant masking operations instruction processing circuits, and related processor systems, methods, and computer-readable media | Melinda J. Brown, Michael William Morrow, James Norris Dieffenderfer, Brian Michael Stempel | 2015-09-29 |
| 8819342 | Methods and apparatus for managing page crossing instructions with different cacheability | Leslie Mark DeBruyne, James Norris Dieffenderfer, Brian Michael Stempel | 2014-08-26 |
| 8661229 | Power efficient instruction prefetch mechanism | Thomas Andrew Sartorius, Victor Roberts Augsburg, James Norris Dieffenderfer, Jeffrey Todd Bridges, Rodney Wayne Smith | 2014-02-25 |
| 8578117 | Write-through-read (WTR) comparator circuits, systems, and methods use of same with a multiple-port file | Gregory Christopher Burda, Nathan Samuel Nunamker, Yeshwant Nagaraj Kolla | 2013-11-05 |
| 8335810 | Register-based shifts for a unidirectional rotator | Anthony D. Klein, Abdulhameed A. Manadath | 2012-12-18 |
| 8127114 | System and method for executing instructions prior to an execution stage in a processor | Kiran Ravi Seth, James Norris Dieffenderfer, Nathan Samuel Nunamaker | 2012-02-28 |
| 7949861 | Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline | James Norris Dieffenderfer, Thomas Andrew Sartorius | 2011-05-24 |
| 7793079 | Method and system for expanding a conditional instruction into a unconditional instruction and a select instruction | Serena Badran-Louca, Rodney Wayne Smith | 2010-09-07 |
| 7725684 | Speculative instruction issue in a simultaneously multithreaded processor | Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith | 2010-05-25 |
| 7698536 | Method and system for providing an energy efficient register file | James Norris Dieffenderfer, Thomas Andrew Sartorius, Jeffrey Todd Bridges, Gregory Christopher Burda | 2010-04-13 |
| 7681022 | Efficient interrupt return address save mechanism | Thomas Andrew Sartorius, Rodney Wayne Smith | 2010-03-16 |
| 7669039 | Use of register renaming system for forwarding intermediate results between constituent instructions of an expanded instruction | James Norris Dieffenderfer, Nathan Samuel Nunamaker, Thomas Andrew Sartorius, Rodney Wayne Smith | 2010-02-23 |
| 7624256 | System and method wherein conditional instructions unconditionally provide output | Thomas Andrew Sartorius, James Norris Dieffenderfer, Jeffrey Todd Bridges, Kenneth Alan Dockser, Rodney Wayne Smith | 2009-11-24 |
| 7624254 | Segmented pipeline flushing for mispredicted branches | Rodney Wayne Smith, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2009-11-24 |
| 7587580 | Power efficient instruction prefetch mechanism | Thomas Andrew Sartorius, Victor Roberts Augsburg, James Norris Dieffenderfer, Jeffrey Todd Bridges, Rodney Wayne Smith | 2009-09-08 |
| 7366877 | Speculative instruction issue in a simultaneously multithreaded processor | Victor Roberts Augsburg, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith | 2008-04-29 |