Issued Patents All Time
Showing 26–50 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6288956 | Semiconductor device having test function | Tetsushi Tanizaki, Tetsuo Kato, Yasuhiro Konishi, Takayuki Miyamoto | 2001-09-11 |
| 6272055 | Semiconductor memory device | Hideto Hidaka, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 2001-08-07 |
| 6269038 | Semiconductor memory device with test mode decision circuit | Takashi Itou, Yasuhiko Tsukikawa, Kengo Aritomi | 2001-07-31 |
| 6249462 | Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit | Koji Tanaka, Jun Nakai, Yasuhiko Tsukikawa | 2001-06-19 |
| 6207998 | Semiconductor device with well of different conductivity types | Satoshi Kawasaki, Kenji Tokami | 2001-03-27 |
| 6197643 | Method for making level converting circuit, internal potential generating circuit and internal potential generating unit | Yuichiro Komiya, Tsukasa Ooishi, Hideto Hidaka | 2001-03-06 |
| 6166989 | Clock synchronous type semiconductor memory device that can switch word configuration | Takeshi Hamamoto, Takuya Ariki, Takayuki Nishiyama | 2000-12-26 |
| 6157588 | Semiconductor memory device having hierarchical word line structure | Yasuhiro Matsumoto, Takeshi Hamamoto, Kei Hamade | 2000-12-05 |
| 6091268 | Potential detecting circuit and semiconductor integrated circuit | Tsukasa Ooishi, Hideto Hidaka | 2000-07-18 |
| 6064607 | Semiconductor memory device with predecoder | Takeo Miki, Satoshi Kawasaki | 2000-05-16 |
| 6064557 | Semiconductor device structured to be less susceptible to power supply noise | Kyoji Yamasaki, Tadaaki Yamauchi | 2000-05-16 |
| 6061808 | Semiconductor memory device having a multibit test mode | Tadaaki Yamauchi, Takashi Ito | 2000-05-09 |
| 6054885 | Semiconductor device and testing apparatus thereof | Tsukasa Ooishi, Tomoya Kawagoe, Hideto Hidaka | 2000-04-25 |
| 6055199 | Test circuit for a semiconductor memory device and method for burn-in test | Kei Hamade, Kiyohiro Furutani, Takashi Kono | 2000-04-25 |
| 6005294 | Method of arranging alignment marks | Takaharu Tsuji, Kyoji Yamasaki | 1999-12-21 |
| 6002621 | Semiconductor memory device | Shinji Tanaka, Koji Tanaka, Kenichi Yasuda | 1999-12-14 |
| 6003148 | Semiconductor memory device allowing repair of a defective memory cell with a redundant circuit in a multibit test mode | Tadaaki Yamauchi, Takashi Ito | 1999-12-14 |
| 5999464 | Semiconductor memory device and method of checking same for defect | Hideto Hidaka, Kiyohiro Furutani, Tetsuo Kato | 1999-12-07 |
| 5978299 | Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation | Kyoji Yamasaki, Tadaaki Yamauchi | 1999-11-02 |
| 5973554 | Semiconductor device structured to be less susceptible to power supply noise | Kyoji Yamasaki, Tadaaki Yamauchi | 1999-10-26 |
| 5972756 | Method of fabricating semiconductor device with a fuse portion | Takashi Kono, Hideto Hidaka, Kenichi Yasuda | 1999-10-26 |
| 5970004 | Semiconductor memory device allowing test regardless of spare cell arrangement | Kazuhiko Takami, Kiyoomi Oshigoe | 1999-10-19 |
| 5969984 | Level converting circuit for converting level of an input signal, internal potential generating circuit for generating internal potential, internal potential generating unit generating internal potential, highly reliable semiconductor device | Yuichiro Komiya, Tsukasa Ooishi, Hideto Hidaka | 1999-10-19 |
| 5970507 | Semiconductor memory device having a refresh-cycle program circuit | Tetsuo Kato, Kiyohiro Furutani, Hideto Hidaka | 1999-10-19 |
| 5966045 | Semiconductor device having a first stage input unit to which a potential is supplied from external and internal power supplies | — | 1999-10-12 |