Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6816422 | Semiconductor memory device having multi-bit testing function | Takashi Kono, Kiyohiro Furutani | 2004-11-09 |
| 6469327 | Semiconductor device with efficiently arranged pads | Kenichi Yasuda, Hideto Hidaka, Mikio Asakura, Tsukasa Ooishi | 2002-10-22 |
| 6449198 | Semiconductor memory device | Takeshi Hamamoto, Masaru Haraguchi, Yasuhiro Konishi | 2002-09-10 |
| 6424142 | Semiconductor device operable in a plurality of test operation modes | Tetsuo Kato | 2002-07-23 |
| 6333879 | Semiconductor device operable in a plurality of test operation modes | Tetsuo Kato | 2001-12-25 |
| 6157588 | Semiconductor memory device having hierarchical word line structure | Yasuhiro Matsumoto, Mikio Asakura, Takeshi Hamamoto | 2000-12-05 |
| 6055199 | Test circuit for a semiconductor memory device and method for burn-in test | Kiyohiro Furutani, Takashi Kono, Mikio Asakura | 2000-04-25 |
| 5953261 | Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output | Kiyohiro Furutani, Tsukasa Ooishi, Mikio Asakura, Hideto Hidaka, Yoshito Nakaoka | 1999-09-14 |
| 5793686 | Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output | Kiyohiro Furutani, Tsukasa Ooishi, Mikio Asakura, Hideto Hidaka, Yoshito Nakaoka | 1998-08-11 |
| 5710737 | Semiconductor memory device | Yuichiro Komiya, Kiyohiro Furutani, Tsukasa Ooishi | 1998-01-20 |
| 5650975 | Semiconductor memory device having improved hierarchical I/O line pair structure | Kenichi Yasuda, Mikio Asakura, Hideto Hidaka | 1997-07-22 |
| 5469402 | Buffer circuit of a semiconductor memory device | Tadaaki Yamauchi, Yoshikazu Morooka | 1995-11-21 |
| 5323349 | Dynamic semiconductor memory device having separate read and write data bases | Shigeru Mori | 1994-06-21 |