Issued Patents All Time
Showing 76–100 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5716889 | Method of arranging alignment marks | Takaharu Tsuji, Kyoji Yamasaki | 1998-02-10 |
| 5715189 | Semiconductor memory device having hierarchical bit line arrangement | — | 1998-02-03 |
| 5708610 | Semiconductor memory device and semiconductor device | Yasuhiko Okasaka, Hideto Hidaka, Masaaki Ura, Fukashi Morishita | 1998-01-13 |
| 5687123 | Semiconductor memory device | Hideto Hidaka, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 1997-11-11 |
| 5682343 | Hierarchical bit line arrangement in a semiconductor memory | Shigeki Tomishima, Masaki Tsukude, Kazuyasu Fujishima | 1997-10-28 |
| 5652730 | Semiconductor memory device having hierarchical boosted power-line scheme | Takashi Kono, Kiyohiro Furutani, Hideto Hidaka | 1997-07-29 |
| 5650975 | Semiconductor memory device having improved hierarchical I/O line pair structure | Kei Hamade, Kenichi Yasuda, Hideto Hidaka | 1997-07-22 |
| 5650972 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Kazutami Arimoto, Hideto Hidaka | 1997-07-22 |
| 5604710 | Arrangement of power supply and data input/output pads in semiconductor memory device | Shigeki Tomishima, Masaki Tsukude, Kazutami Arimoto | 1997-02-18 |
| 5602793 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Kazutami Arimoto, Hideto Hidaka | 1997-02-11 |
| 5588130 | Semiconductor memory device for simple cache system | Kazuyasu Fujishima, Yoshio Matsuda | 1996-12-24 |
| 5509132 | Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof | Yoshio Matsuda, Kazuyasu Fujishima, Hideto Hidaka | 1996-04-16 |
| 5495440 | Semiconductor memory device having hierarchical bit line structure | — | 1996-02-27 |
| 5426615 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Kazutami Arimoto, Hideto Hidaka | 1995-06-20 |
| 5353427 | Semiconductor memory device for simple cache system with selective coupling of bit line pairs | Kazuyasu Fujishima, Yoshio Matsuda | 1994-10-04 |
| 5325336 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Kazutami Arimoto, Hideto Hidaka | 1994-06-28 |
| 5321646 | Layout of a semiconductor memory device | Shigeki Tomishima, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi | 1994-06-14 |
| 5315548 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai +4 more | 1994-05-24 |
| 5303183 | Semiconductor memory device | — | 1994-04-12 |
| 5249155 | Semiconductor device incorporating internal voltage down converting circuit | Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Masaki Tsukude, Shinji Kawai +1 more | 1993-09-28 |
| 5226139 | Semiconductor memory device with a built-in cache memory and operating method thereof | Kazuyasu Fujishima, Yoshio Matsuda, Hideto Hidaka | 1993-07-06 |
| 5226147 | Semiconductor memory device for simple cache system | Kazuyasu Fujishima, Yoshio Matsuda | 1993-07-06 |
| 5179687 | Semiconductor memory device containing a cache and an operation method thereof | Hideto Hidaka, Kazuyasu Fujishima, Yoshio Matsuda | 1993-01-12 |
| 5091887 | Dynamic semiconductor memory device | — | 1992-02-25 |
| 5014241 | Dynamic semiconductor memory device having reduced soft error rate | Kazuyasu Fujishima, Yoshio Matsuda | 1991-05-07 |