Issued Patents All Time
Showing 1–25 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6859403 | Semiconductor memory device capable of overcoming refresh disturb | Hideto Hidaka, Mikio Asakura, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 2005-02-22 |
| 6414883 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 2002-07-02 |
| 6404056 | Semiconductor integrated circuit | Shigehiro Kuge, Kazutami Arimoto, Masaki Tsukude | 2002-06-11 |
| 6404691 | Semiconductor memory device for simple cache system | Yoshio Matsuda, Mikio Asakura | 2002-06-11 |
| 6272055 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 2001-08-07 |
| 6214664 | Method of manufacturing semiconductor device | Hiroshi Kimura, Tadashi Nishimura, Takahiro Tsuruda, Kazutami Arimoto, Tadato Yamagata | 2001-04-10 |
| 6075732 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude | 2000-06-13 |
| 6069379 | Semiconductor device and method of manufacturing the same | Hiroshi Kimura, Tadashi Nishimura, Takahiro Tsuruda, Kazutami Arimoto, Tadato Yamagata | 2000-05-30 |
| 5982678 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude | 1999-11-09 |
| 5969420 | Semiconductor device comprising a plurality of interconnection patterns | Shigehiro Kuge, Kazutami Arimoto, Masaki Tsukude | 1999-10-19 |
| 5943273 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 1999-08-24 |
| 5894440 | Semiconductor memory device and data transferring structure and method therein | Masaki Tsukude, Kazutami Arimoto, Yoshio Matsuda, Tsukasa Ooishi | 1999-04-13 |
| RE36089 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai +4 more | 1999-02-09 |
| RE36027 | Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages | Kazutami Arimoto, Hideto Hidaka, Masaki Tsukude, Tsukasa Ohishi | 1999-01-05 |
| 5687123 | Semiconductor memory device | Hideto Hidaka, Mikio Asakura, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 1997-11-11 |
| 5682343 | Hierarchical bit line arrangement in a semiconductor memory | Shigeki Tomishima, Masaki Tsukude, Mikio Asakura | 1997-10-28 |
| 5588130 | Semiconductor memory device for simple cache system | Yoshio Matsuda, Mikio Asakura | 1996-12-24 |
| 5550769 | Bit line structure for semiconductor memory device | Hideto Hidaka, Yoshio Matsuda | 1996-08-27 |
| 5509132 | Semiconductor memory device having an SRAM as a cache memory integrated on the same chip and operating method thereof | Yoshio Matsuda, Hideto Hidaka, Mikio Asakura | 1996-04-16 |
| 5504713 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude | 1996-04-02 |
| RE35141 | Substrate bias generating circuit | Hideyuki Ozaki, Kazuhiro Shimotori | 1996-01-09 |
| 5461589 | Bit line structure for semiconductor memory device with bank separation at cross-over regions | Hideto Hidaka, Yoshio Matsuda | 1995-10-24 |
| 5416734 | Bit line structure for semiconductor memory device | Hideto Hidaka, Yoshio Matsuda | 1995-05-16 |
| 5371714 | Method and apparatus for driving word line in block access memory | Yoshio Matsuda, Hideto Hidaka | 1994-12-06 |
| 5353427 | Semiconductor memory device for simple cache system with selective coupling of bit line pairs | Yoshio Matsuda, Mikio Asakura | 1994-10-04 |