Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7365578 | Semiconductor device with pump circuit | Minoru Senda, Kiyohiro Furutani, Taku Ogura, Satoshi Kawasaki, Tadaaki Yamauchi | 2008-04-29 |
| 7268612 | Semiconductor device with pump circuit | Minoru Senda, Kiyohiro Furutani, Taku Ogura, Satoshi Kawasaki, Tadaaki Yamauchi | 2007-09-11 |
| 7180362 | Semiconductor device with pump circuit | Minoru Senda, Kiyohiro Furutani, Taku Ogura, Satoshi Kawasaki, Tadaaki Yamauchi | 2007-02-20 |
| 7157773 | Nonvolatile semiconductor memory device | Hiroshi Kato, Hideyuki Noda, Fukashi Morishita, Shuichi Ueno | 2007-01-02 |
| 6962827 | Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device | Katsuya Furue, Shigeru Kikuda, Kiyohiro Furutani, Tetsushi Tanizaki, Takashi Kono | 2005-11-08 |
| 6897523 | Semiconductor device | Shuichi Ueno, Haruo Furuta, Hiroshi Kato | 2005-05-24 |
| 6850454 | Semiconductor memory device with reduced current consumption during standby state | Takeshi Hamamoto | 2005-02-01 |
| 6809975 | Semiconductor memory device having test mode and memory system using the same | Shigeru Yamaoka | 2004-10-26 |
| 6781900 | Semiconductor memory device with enhanced reliability | Kiyohiro Furutani, Takeshi Hamamoto, Takashi Kubo | 2004-08-24 |
| 6777976 | Interface circuit and semiconductor device with the same | — | 2004-08-17 |
| 6731535 | Nonvolatile semiconductor memory device | Tsukasa Ooishi, Shuichi Ueno | 2004-05-04 |
| 6715096 | Interface circuit device for performing data sampling at optimum strobe timing by using stored data window information to determine the strobe timing | — | 2004-03-30 |
| 6466496 | Semiconductor integrated circuit having circuit for data transmission distance measurement and memory processing system with the same | — | 2002-10-15 |
| 6438067 | Clock generating circuit ensuring a wide lock-allowing frequency range and allowing reduction in layout area as well as a semiconductor device provided with the same | Takeshi Hamamoto | 2002-08-20 |
| 6424593 | Semiconductor memory device capable of adjusting internal parameter | Tetsuo Kato | 2002-07-23 |
| 6414891 | Semiconductor device including complementary data bus pair | Takeshi Hamamoto | 2002-07-02 |
| 6404056 | Semiconductor integrated circuit | Kazutami Arimoto, Masaki Tsukude, Kazuyasu Fujishima | 2002-06-11 |
| 6388329 | Semiconductor integrated circuit having three wiring layers | Kazutami Arimoto | 2002-05-14 |
| 6351169 | Internal clock signal generating circuit permitting rapid phase lock | — | 2002-02-26 |
| 6339553 | Clock generating circuit having additional delay line outside digital DLL loop and semiconductor memory device including the same | — | 2002-01-15 |
| 6157052 | Semiconductor integrated circuit having three wiring layers | Kazutami Arimoto | 2000-12-05 |
| 5969420 | Semiconductor device comprising a plurality of interconnection patterns | Kazutami Arimoto, Masaki Tsukude, Kazuyasu Fujishima | 1999-10-19 |
| 5847420 | Semiconductor integrated circuit having three wiring layers | Kazutami Arimoto | 1998-12-08 |
| 5818772 | Semiconductor memory devices having a built-in test function | — | 1998-10-06 |
| 5604707 | Semiconductor memory device responsive to hierarchical internal potentials | Shigeki Tomishima, Kazutami Arimoto, Hideto Hidaka, Takahiro Tsuruda | 1997-02-18 |