Issued Patents All Time
Showing 1–21 of 21 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6962827 | Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device | Katsuya Furue, Kiyohiro Furutani, Tetsushi Tanizaki, Shigehiro Kuge, Takashi Kono | 2005-11-08 |
| 6301169 | Semiconductor memory device with IO compression test mode | Takeshi Hamamoto, Mikio Asakura | 2001-10-09 |
| 6166415 | Semiconductor device with improved noise resistivity | Kazuhiro Sakemi, Satoshi Kawasaki | 2000-12-26 |
| 6091651 | Semiconductor memory device with improved test efficiency | Kiyohiro Furutani, Takeshi Hamamoto | 2000-07-18 |
| 5903575 | Semiconductor memory device having fast data writing mode and method of writing testing data in fast data writing mode | — | 1999-05-11 |
| 5767929 | Liquid crystal display apparatus with shorting ring | Shigeru Yachi, Naoki Nakagawa | 1998-06-16 |
| 5586076 | Semiconductor memory device permitting high speed data transfer and high density integration | Hiroshi Miyamoto, Yoshikazu Morooka, Kiyohiro Furutani | 1996-12-17 |
| 5574729 | Redundancy circuit for repairing defective bits in semiconductor memory device | Mitsuya Kinoshita, Shigeru Mori, Yoshikazu Morooka, Hiroshi Miyamoto, Makoto Suwa | 1996-11-12 |
| 5519243 | Semiconductor device and manufacturing method thereof | Kiyohiro Furutani, Makoto Suwa | 1996-05-21 |
| 5448516 | Semiconductor memory device suitable for high integration | Yasuhiko Tsukikawa, Hiroshi Miyamoto | 1995-09-05 |
| 5384784 | Semiconductor memory device comprising a test circuit and a method of operation thereof | Shigeru Mori, Makoto Suwa, Hiroshi Miyamoto, Yoshikazu Morooka, Mitsuya Kinoshita | 1995-01-24 |
| 5357478 | Semiconductor integrated circuit device including a plurality of cell array blocks | Shigeru Mori, Yoshikazu Morooka, Hiroshi Miyamoto, Makoto Suwa, Mitsuya Kinoshita | 1994-10-18 |
| 5323348 | Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit | Shigeru Mori, Yoshikazu Morooka, Hiroshi Miyamoto, Mitsuya Kinoshita, Makoto Suwa +1 more | 1994-06-21 |
| 5321654 | Semiconductor device having no through current flow in standby period | Hiroshi Miyamoto, Yoshikazu Morooka, Shigeru Mori, Makoto Suwa, Mitsuya Kinoshita | 1994-06-14 |
| 5227997 | Semiconductor circuit device having multiplex selection functions | Takeshi Hamamoto | 1993-07-13 |
| 5146429 | Semiconductor memory device including a redundancy circuitry for repairing a defective memory cell and a method for repairing a defective memory cell | Shinji Kawai, Shigeru Mori | 1992-09-08 |
| 5063313 | Delay circuit employing different threshold FET's | Hiroshi Miyamoto, Michihiro Yamada | 1991-11-05 |
| 4994689 | Semiconductor integrated circuit device | Hiroshi Miyamoto | 1991-02-19 |
| 4931668 | MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform | Michihiro Yamada, Hiroshi Miyamoto | 1990-06-05 |
| 4914326 | Delay circuit | Hiroshi Miyamoto, Michihiro Yamada | 1990-04-03 |
| 4879679 | Dynamic random access memory having storage gate electrode grounding means | Hiroshi Miyamoto | 1989-11-07 |