Issued Patents All Time
Showing 1–25 of 41 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11200945 | Semiconductor memory device | Takashi Kubo, Masaru Haraguchi, Takeshi Hamamoto, Kenichi Yasuda, Hironori Iga | 2021-12-14 |
| 10991418 | Semiconductor memory device comprising an interface conforming to JEDEC standard and control device therefor | Masaru Haraguchi, Takashi Kubo, Hironori Iga, Kenichi Yasuda, Takeshi Hamamoto | 2021-04-27 |
| 7288965 | Semiconductor device and level conversion circuit | Kyoji Yamasaki | 2007-10-30 |
| 7161387 | Semiconductor device and level conversion circuit | Kyoji Yamasaki | 2007-01-09 |
| 7102935 | Semiconductor memory device driven with low voltage | Takeo Miki, Shinji Tanaka | 2006-09-05 |
| 7072204 | Semiconductor memory device having dummy word line | Takashi Ito | 2006-07-04 |
| 6934204 | Semiconductor device with reduced terminal input capacitance | Takashi Itou | 2005-08-23 |
| 6903961 | Semiconductor memory device having twin-cell units | Takashi Ito | 2005-06-07 |
| 6867994 | Semiconductor memory device with memory cells arranged in high density | — | 2005-03-15 |
| 6787859 | Semiconductor memory device with shortened connection length among memory block, data buffer and data bus | Takashi Itou, Masaki Shimoda | 2004-09-07 |
| 6735133 | Semiconductor memory circuit having normal operation mode and burn-in test mode | — | 2004-05-11 |
| 6727738 | Configuration for generating a clock including a delay circuit and method thereof | — | 2004-04-27 |
| 6717841 | Semiconductor memory device having nonvolatile memory cell of high operating stability | — | 2004-04-06 |
| 6700406 | Multi-valued logical circuit with less latch-up | — | 2004-03-02 |
| 6687174 | Semiconductor memory device capable of switching output data width | Yukiko Maruyama, Mikio Asakura, Takashi Itou | 2004-02-03 |
| 6535412 | Semiconductor memory device capable of switching output data width | Yukiko Maruyama, Mikio Asakura, Takashi Itou | 2003-03-18 |
| 6469952 | Semiconductor memory device capable of reducing power supply voltage in a DRAM's word driver | — | 2002-10-22 |
| 6304496 | Semiconductor memory device with write driver reset function | — | 2001-10-16 |
| 6285602 | Semiconductor memory device provided with I/O clamp circuit | Susumu Tanida | 2001-09-04 |
| 6269038 | Semiconductor memory device with test mode decision circuit | Takashi Itou, Kengo Aritomi, Mikio Asakura | 2001-07-31 |
| 6249462 | Data output circuit that can drive output data speedily and semiconductor memory device including such a data output circuit | Koji Tanaka, Jun Nakai, Mikio Asakura | 2001-06-19 |
| 6201748 | Semiconductor memory device having test mode | Yayoi Nakamura, Koji Tanaka | 2001-03-13 |
| 6121812 | Delay circuit having delay time free from influence of operation environment | — | 2000-09-19 |
| 6061285 | Semiconductor memory device capable of executing earlier command operation in test mode | — | 2000-05-09 |
| 6005434 | Substrate potential generation circuit that can suppress variation of output voltage with respect to change in external power supply voltage and environment temperature | Tsukasa Ooishi | 1999-12-21 |