Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8446765 | Semiconductor memory device having memory block configuration | Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo | 2013-05-21 |
| 8208303 | Semiconductor memory device having memory block configuration | Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo | 2012-06-26 |
| 8000159 | Semiconductor memory device having memory block configuration | Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo | 2011-08-16 |
| 7782672 | Semiconductor memory device having memory block configuration | Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo | 2010-08-24 |
| 7447087 | Semiconductor memory device having memory block configuration | Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo | 2008-11-04 |
| 7248513 | Semiconductor memory device having memory block configuration | Taku Ogura, Tadaaki Yamauchi, Hidenori Mitani, Takashi Kubo | 2007-07-24 |
| 6597624 | Semiconductor memory device having hierarchical word line structure | — | 2003-07-22 |
| 6504744 | Semiconductor memory device with memory test circuit | Mikio Asakura | 2003-01-07 |
| 6477105 | Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver | Mikio Asakura, Takashi Ito, Kiyohiro Furutani | 2002-11-05 |
| 6407942 | Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver | Mikio Asakura, Takashi Ito, Kiyohiro Furutani | 2002-06-18 |
| 6344763 | Semiconductor integrated circuit device that can suppress generation of signal skew between data input/output terminals | Takayuki Miyamoto | 2002-02-05 |
| 6269038 | Semiconductor memory device with test mode decision circuit | Takashi Itou, Yasuhiko Tsukikawa, Mikio Asakura | 2001-07-31 |