Issued Patents All Time
Showing 1–25 of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5882780 | Elastic polyester fibers and stretchable fiber articles containing same | Yasuo Yamamura, Mikio Tashiro, Yasuyuki Yamazaki, Takeshi Honjou, Nobuyuki Yamamoto | 1999-03-16 |
| 5690858 | Mesomorphic compound, liquid crystal composition and liquid crystal device | Hiroyuki Nohira, Kazuo Yoshinaga | 1997-11-25 |
| 5481496 | Semiconductor memory device and method of data transfer therefor | Toshifumi Kobayashi, Yoshikazu Morooka, Takeshi Hamamoto | 1996-01-02 |
| 5323348 | Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit | Shigeru Mori, Yoshikazu Morooka, Hiroshi Miyamoto, Mitsuya Kinoshita, Makoto Suwa +1 more | 1994-06-21 |
| 5305261 | Semiconductor memory device and method of testing the same | Kiyohiro Furutani, Shigeru Mori | 1994-04-19 |
| 5208474 | Input circuit of a semiconductor device | Tadato Yamagata, Hiroshi Miyamoto | 1993-05-04 |
| 5112771 | Method of fibricating a semiconductor device having a trench | Tatsuya Ishii, Yoji Mashiko, Masao Nagatomo | 1992-05-12 |
| 5073874 | Method of and apparatus for reducing current of semiconductor memory device | Hiroshi Miyamoto | 1991-12-17 |
| 5063313 | Delay circuit employing different threshold FET's | Shigeru Kikuda, Hiroshi Miyamoto | 1991-11-05 |
| 5053997 | Dynamic random access memory with FET equalization of bit lines | Hiroshi Miyamato | 1991-10-01 |
| 5019883 | Input protective apparatus of semiconductor device | Shigeru Mori, Hideshi Miyatake, Shuji Murakami | 1991-05-28 |
| 4984054 | Electric fuse for a redundancy circuit | Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori | 1991-01-08 |
| 4962379 | Arbiter circuit for processing concurrent requests for access to shared resources | Kenichi Yasuda, Toshifumi Kobayashi | 1990-10-09 |
| 4933902 | Method of and apparatus for reducing current of semiconductor memory device | Hiroshi Miyamoto | 1990-06-12 |
| 4931668 | MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform | Shigeru Kikuda, Hiroshi Miyamoto | 1990-06-05 |
| 4914326 | Delay circuit | Shigeru Kikuda, Hiroshi Miyamoto | 1990-04-03 |
| 4904885 | Substrate bias circuit having substrate bias voltage clamp and operating method therefor | Hiroshi Miyamoto, Tadato Yamagata, Shigeru Mori, Tetsuya Aono | 1990-02-27 |
| 4870620 | Dynamic random access memory device with internal refresh | Tadato Yamagata, Hiroshi Miyamoto, Shigeru Mori, Tetsuya Aono | 1989-09-26 |
| 4855613 | Wafer scale integration semiconductor device having improved chip power-supply connection arrangement | Hiroshi Miyamoto | 1989-08-08 |
| 4803663 | Semiconductor memory having divided bit lines and individual sense amplifiers | Hiroshi Miyamoto | 1989-02-07 |
| 4792927 | Semiconductor memory device with bit line sense amplifiers | Hiroshi Miyamoto | 1988-12-20 |
| 4788455 | CMOS reference voltage generator employing separate reference circuits for each output transistor | Shigeru Mori, Hiroshi Miyamoto, Tadato Yamagata, Kazutami Arimoto | 1988-11-29 |
| 4780850 | CMOS dynamic random access memory | Hiroshi Miyamoto, Shigeru Mori, Tadato Yamagata | 1988-10-25 |
| 4739500 | Dynamic ram having folded bit line structure | Hiroshi Miyamoto | 1988-04-19 |
| 4724341 | CMOS decoder circuit resistant to latch-up | Hiroshi Miyamoto | 1988-02-09 |