Issued Patents All Time
Showing 26–50 of 93 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5321657 | Random access memory of a CSL system with a bit line pair and an I/O line pair independently set to different precharge voltages | Kazutami Arimoto, Hideto Hidaka, Masaki Tsukude, Tsukasa Ohishi | 1994-06-14 |
| 5315548 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai +4 more | 1994-05-24 |
| 5289417 | Semiconductor memory device with redundancy circuit | Tsukasa Ooishi, Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude | 1994-02-22 |
| 5283762 | Semiconductor device containing voltage converting circuit and operating method thereof | — | 1994-02-01 |
| 5280443 | Bit line structure for semiconductor memory device | Hideto Hidaka, Yoshio Matsuda | 1994-01-18 |
| RE34463 | Semiconductor memory device with active pull up | Yasuhiro Konishi, Masaki Kumanoya, Hideshi Miyatake, Hideto Hidaka, Katsumi Dosaka | 1993-11-30 |
| 5267214 | Shared-sense amplifier control signal generating circuit in dynamic type semiconductor memory device and operating method therefor | Yoshio Matsuda, Kazutami Arimoto, Tsukasa Ooishi, Masaki Tsukude | 1993-11-30 |
| 5250458 | Method for manufacturing semiconductor memory device having stacked memory capacitors | Katsuhiro Tsukamoto, Masahiro Shimizu, Yoshio Matsuda | 1993-10-05 |
| 5226147 | Semiconductor memory device for simple cache system | Yoshio Matsuda, Mikio Asakura | 1993-07-06 |
| 5226139 | Semiconductor memory device with a built-in cache memory and operating method thereof | Yoshio Matsuda, Hideto Hidaka, Mikio Asakura | 1993-07-06 |
| 5222047 | Method and apparatus for driving word line in block access memory | Yoshio Matsuda, Hideto Hidaka | 1993-06-22 |
| 5214601 | Bit line structure for semiconductor memory device including cross-points and multiple interconnect layers | Hideto Hidaka, Yoshio Matsuda | 1993-05-25 |
| 5189316 | Stepdown voltage generator having active mode and standby mode | Shuji Murakami | 1993-02-23 |
| 5185744 | Semiconductor memory device with test circuit | Kazutami Arimoto, Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude | 1993-02-09 |
| 5184327 | Semiconductor memory device having on-chip test circuit and method for testing the same | Yoshio Matsuda, Kazutami Arimoto, Tsukasa Ooishi, Masaki Tsukude | 1993-02-02 |
| 5179687 | Semiconductor memory device containing a cache and an operation method thereof | Hideto Hidaka, Yoshio Matsuda, Mikio Asakura | 1993-01-12 |
| 5136543 | Data descrambling in semiconductor memory device | Yoshio Matsuda, Kazutami Arimoto, Masaki Tsukude, Tsukasa Oishi | 1992-08-04 |
| 5111386 | Cache contained type semiconductor memory device and operating method therefor | Charles Hart | 1992-05-05 |
| 5103426 | Decoding circuit and method for functional block selection | Hideto Hidaka, Yoshio Matsuda | 1992-04-07 |
| 5088063 | Semiconductor memory device having on-chip test circuit | Yoshio Matsuda, Kazutami Arimoto, Tsukasa Ooishi, Masaki Tsukude | 1992-02-11 |
| 5077688 | Semiconductor memory device having improved memory cells provided with cylindrical type capacitors | Masaki Kumanoya | 1991-12-31 |
| 5060230 | On chip semiconductor memory arbitrary pattern, parallel test apparatus and method | Kazutami Arimoto, Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude | 1991-10-22 |
| 5030586 | Method for manufacturing semiconductor memory device having improved resistance to .alpha. particle induced soft errors | Yoshio Matsuda | 1991-07-09 |
| 5022007 | Test signal generator for semiconductor integrated circuit memory and testing method thereof | Kazutami Arimoto, Yoshio Matsuda, Tsukasa Ooishi, Masaki Tsukude | 1991-06-04 |
| 5014241 | Dynamic semiconductor memory device having reduced soft error rate | Mikio Asakura, Yoshio Matsuda | 1991-05-07 |