Issued Patents All Time
Showing 51–75 of 103 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5953261 | Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output | Kiyohiro Furutani, Tsukasa Ooishi, Hideto Hidaka, Kei Hamade, Yoshito Nakaoka | 1999-09-14 |
| 5943273 | Semiconductor memory device | Hideto Hidaka, Kazuyasu Fujishima, Tsukasa Ooishi, Kazutami Arimoto, Shigeki Tomishima +1 more | 1999-08-24 |
| 5917766 | Semiconductor memory device that can carry out read disturb testing and burn-in testing reliably | Takaharu Tsuji, Tadaaki Yamauchi, Koji Tanaka | 1999-06-29 |
| 5898316 | Mode setting circuit of semiconductor device | Tetsuo Kato, Tsukasa Ooishi, Hideto Hidaka | 1999-04-27 |
| 5875145 | Semiconductor memory device having a voltage lowering circuit of which supplying capability increases when column system is in operation | Kyoji Yamasaki, Tadaaki Yamauchi | 1999-02-23 |
| RE36089 | Column selecting circuit in semiconductor memory device | Tsukasa Ooishi, Kazutami Arimoto, Hideto Hidaka, Masanori Hayashikoshi, Shinji Kawai +4 more | 1999-02-09 |
| 5867418 | Semiconductor memory device and semiconductor device | Yasuhiko Okasaka, Hideto Hidaka, Masaaki Ura, Fukashi Morishita | 1999-02-02 |
| 5867439 | Semiconductor memory device having internal address converting function, whose test and layout are conducted easily | Hideto Hidaka, Kiyohiro Furutani, Kenichi Yasuda | 1999-02-02 |
| 5859799 | Semiconductor memory device including internal power supply circuit generating a plurality of internal power supply voltages at different levels | Yasuhiro Matsumoto, Kouji Tanaka, Kyoji Yamasaki | 1999-01-12 |
| 5844767 | Level converting circuit for converting level of an input signal, internal potential generating circuit for generating internal potential, internal potential generating unit generating internal potential highly reliable semiconductor device and method of | Yuichiro Komiya, Tsukasa Ooishi, Hideto Hidaka | 1998-12-01 |
| 5838627 | Arrangement of power supply and data input/output pads in semiconductor memory device | Shigeki Tomishima, Masaki Tsukude, Kazutami Arimoto | 1998-11-17 |
| 5828258 | Semiconductor device and testing apparatus thereof | Tsukasa Ooishi, Tomoya Kawagoe, Hideto Hidaka | 1998-10-27 |
| 5815454 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Kazutami Arimoto, Hideto Hidaka | 1998-09-29 |
| 5812492 | Control signal generation circuit and semiconductor memory device that can correspond to high speed external clock signal | Tadaaki Yamauchi, Takaharu Tsuji | 1998-09-22 |
| 5793686 | Semiconductor memory device having data input/output circuit of small occupied area capable of high-speed data input/output | Kiyohiro Furutani, Tsukasa Ooishi, Hideto Hidaka, Kei Hamade, Yoshito Nakaoka | 1998-08-11 |
| 5789808 | Semiconductor device structured to be less susceptible to power supply noise | Kyoji Yamasaki, Tadaaki Yamauchi | 1998-08-04 |
| 5781484 | Semiconductor memory device | Koji Tanaka, Kenichi Yasuda | 1998-07-14 |
| 5764576 | Semiconductor memory device and method of checking same for defect | Hideto Hidaka, Kiyohiro Furutani, Tetsuo Kato | 1998-06-09 |
| 5760614 | Potential detecting circuit and semiconductor integrated circuit | Tsukasa Ooishi, Hideto Hidaka | 1998-06-02 |
| 5757711 | Amplifier circuit and complementary amplifier circuit with limiting function for output lower limit | Yoshito Nakaoka, Kiyohiro Furutani | 1998-05-26 |
| 5748549 | Semiconductor memory device | Osamu Kometani, Shoichi Wakano | 1998-05-05 |
| 5740119 | Semiconductor memory device having internal address converting function, whose test and layout are conducted easily | Hideto Hidaka, Kiyohiro Furutani, Kenichi Yasuda | 1998-04-14 |
| 5732034 | Semiconductor memory device having an address key circuit for reducing power consumption | Tadaaki Yamauchi, Takashi Ito | 1998-03-24 |
| 5726940 | Semiconductor memory device of which prescribed state of operation is terminated under a prescribed condition and method of operating a semiconductor memory device for terminating prescribed state of operation | Hideto Hidaka, Kiyohiro Furutani | 1998-03-10 |
| 5724293 | Semiconductor memory device having power line arranged in a meshed shape | Shigeki Tomishima, Kazutami Arimoto, Hideto Hidaka | 1998-03-03 |