Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10540584 | Queue management for direct memory access | Amol Ashok Ambardekar, Kent D. Cedola, George Petre, Larry Marvin Wall, Boris Bobrov | 2020-01-21 |
| 10528494 | Direct memory access (“DMA”) descriptor processing using identifiers assigned to descriptors on DMA engines | Jeffrey Powers Bradford, Steven Wheeler, Christopher Jon Johnson, Boris Bobrov, Andras Tantos | 2020-01-07 |
| 9715464 | Direct memory access descriptor processing | Jeffrey Powers Bradford, Steven Wheeler, Christopher Jon Johnson, Boris Bobrov, Andras Tantos | 2017-07-25 |
| 9405315 | Delayed execution of program code on multiple processors | Mark David Bellows, Mark S. Fredrickson, Scott D. Frei, Steven P. Jones | 2016-08-02 |
| 9146835 | Methods and systems with delayed execution of multiple processors | Mark David Bellows, Mark S. Fredrickson, Scott D. Frei, Steven P. Jones | 2015-09-29 |
| 8589630 | Methods and apparatus for handling a cache miss | John D. Irish, Andrew Henry Wottreng | 2013-11-19 |
| 8327075 | Methods and apparatus for handling a cache miss | John D. Irish, Andrew Henry Wottreng | 2012-12-04 |
| 8196074 | Heuristic clustering of circuit elements in a circuit design | Mark S. Fredrickson, Glen Howard Handlogten | 2012-06-05 |
| 8127082 | Method and apparatus for allowing uninterrupted address translations while performing address translation cache invalidates and other cache operations | Andrew Henry Wottreng, John D. Irish | 2012-02-28 |
| 7917700 | Method and cache control circuit for replacing cache lines using alternate PLRU algorithm and victim cache coherency state | John D. Irish, Jack Chris Randolph | 2011-03-29 |
| 7716423 | Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes | John D. Irish, Andrew Henry Wottreng | 2010-05-11 |
| 7634591 | Method and apparatus for tracking command order dependencies | John D. Irish | 2009-12-15 |
| 7543204 | Method, apparatus and computer program product for designing logic scan chains for matching gated portions of a clock tree | Mark S. Fredrickson, Glen Howard Handlogten, Steven P. Jones | 2009-06-02 |
| 7539840 | Handling concurrent address translation cache misses and hits under those misses while maintaining command order | John D. Irish, Ibrahim Abdel-Rahman Ouda, Andrew Henry Wottreng | 2009-05-26 |
| 7509611 | Heuristic clustering of circuit elements in a circuit design | Mark S. Fredrickson, Glen Howard Handlogten | 2009-03-24 |
| 7472227 | Invalidating multiple address cache entries | Andrew Henry Wottreng | 2008-12-30 |
| 7458174 | Needle punch stretch hoop | Clella Gustin, Jared Burton, Gerry Ayala | 2008-12-02 |
| 7430699 | Trading propensity-based clustering of circuit elements in a circuit design | Mark S. Fredrickson | 2008-09-30 |
| 7398505 | Automatic back annotation of a functional definition of an integrated circuit design based upon physical layout | Mark S. Fredrickson, Glen Howard Handlogten | 2008-07-08 |
| 7330479 | Shared transmit buffer for network processor and methods for using same | Kenneth J. Barker | 2008-02-12 |
| 7149218 | Cache line cut through of limited life data in a data processing system | Jonathan Byrn, Robert Neal Carlton Broberg, III, Gary McClannahan | 2006-12-12 |
| 6836767 | Pipelined hardware implementation of a neural network circuit | — | 2004-12-28 |
| 6601122 | Exceptions and interrupts with dynamic priority and vector routing | Robert Neal Carlton Broberg, III, Jonathan Byrn, Gary McClannahan | 2003-07-29 |
| 6453366 | Method and apparatus for direct memory access (DMA) with dataflow blocking for users | Robert Neal Carlton Broberg, III, Jonathan Byrn, Gary McClannahan | 2002-09-17 |
| 6289430 | Method and apparatus for target addressing and translation in a non-uniform memory environment with user defined target tags | Robert Neal Carlton Broberg, III, Jonathan Byrn, Gary McClannahan | 2001-09-11 |