WT

Wuu Yean Tay

Micron: 29 patents #636 of 6,345Top 15%
📍 Singapore, SG: #167 of 13,971 inventorsTop 2%
Overall (All Time): #131,088 of 4,157,543Top 4%
29
Patents All Time

Issued Patents All Time

Showing 1–25 of 29 patents

Patent #TitleCo-InventorsDate
11189548 Pre-encapsulated lead frames for microelectronic device packages, and associated methods Ai Chie Wang, Choon Kuan Lee, Chin Hui Chong 2021-11-30
9721874 Pre-encapsulated lead frames for microelectronic device packages, and associated methods Ai Chie Wang, Choon Kuan Lee, Chin Hui Chong 2017-08-01
8525320 Microelectronic die packages with leadframes, including leadframe-based interposer for stacked die packages, and associated systems and methods Meow Koon Eng, Yong Poo Chia, Suan Jeung Boon 2013-09-03
8357566 Pre-encapsulated lead frames for microelectronic device packages, and associated methods Ai Chie Wang, Choon Kuan Lee, Chin Hui Chong 2013-01-22
7915718 Apparatus for flip-chip packaging providing testing capability Teck Kheng Lee, Kian Lee 2011-03-29
7820459 Methods relating to the reconstruction of semiconductor wafers for wafer level processing including forming of alignment protrusion and removal of alignment material Yong Kian Tan 2010-10-26
7754531 Method for packaging microelectronic devices Cher Khng Victor Tan 2010-07-13
7573006 Apparatus relating to the reconstruction of semiconductor wafers for wafer-level processing Yong Kian Tan 2009-08-11
7425462 Methods relating to the reconstruction of semiconductor wafers for wafer-level processing Yong Kian Tan 2008-09-16
7368391 Methods for designing carrier substrates with raised terminals Cher Khng Victor Tan, Choon Kuan Lee, Kian Lee, Guek Har Lim, Teck Huat Poh +1 more 2008-05-06
7285971 Integrated circuit (IC) test assembly including phase change material for stabilizing temperature during stress testing of integrated circuits and method thereof Pak Hong Yee 2007-10-23
7190074 Reconstructed semiconductor wafers including alignment droplets contacting alignment vias Yong Kian Tan 2007-03-13
7116122 Method for ball grid array chip packages having improved testing and stacking characteristics Jeffrey Toh Tuck Fook 2006-10-03
7071012 Methods relating to the reconstruction of semiconductor wafers for wafer-level processing Yong Kian Tan 2006-07-04
7061124 Solder masks including dams for at least partially surrounding terminals of a carrier substrate and recessed areas positioned adjacent to the dams, and carrier substrates including such solder masks Cher Khng Victor Tan, Choon Kuan Lee, Kian Lee, Guek Har Lim, Teck Huat Poh +1 more 2006-06-13
7030640 Integrated circuit (IC) test assembly including phase change material for stabilizing temperature during stress testing of integrated circuits and method thereof Pak Hong Yee 2006-04-18
7018871 Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks, and methods Cher Khng Victor Tan, Choon Kuan Lee, Kian Lee, Guek Har Lim, Teck Huat Poh +1 more 2006-03-28
6856155 Methods and apparatus for testing and burn-in of semiconductor devices Yong Kian Tan, Yong Poo Chia, Siu Waf Low, Suan Jeung Boon, Soon Huat Goh 2005-02-15
6847220 Method for ball grid array chip packages having improved testing and stacking characteristics Jeffrey Toh Tuck Fook 2005-01-25
6787923 Solder masks for use on carrier substrates, carrier substrates and semiconductor device assemblies including such solder masks Cher Khng Victor Tan, Choon Kuan Lee, Kian Lee, Guek Har Lim, Teck Huat Poh +1 more 2004-09-07
6740984 Ball grid array chip packages having improved testing and stacking characteristics Jeffrey Toh Tuck Fook 2004-05-25
6740983 Method for ball grind array chip packages having improved testing and stacking characteristics Jeffrey Toh Tuck Fook 2004-05-25
6693363 Ball grid array chip packages having improved testing and stacking characteristics Jeffrey Toh Tuck Fook 2004-02-17
6674175 Ball grid array chip packages having improved testing and stacking characteristics Jeffrey Toh Tuck Fook 2004-01-06
6600335 Method for ball grid array chip packages having improved testing and stacking characteristics Jeffrey Toh Tuck Fook 2003-07-29