Issued Patents All Time
Showing 276–300 of 303 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5229331 | Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology | Trung T. Doan, J. Brett Rolfson, David A. Cathey | 1993-07-20 |
| 5223734 | Semiconductor gettering process using backside chemical mechanical planarization (CMP) and dopant diffusion | Trung T. Doan, Gurtej S. Sandhu | 1993-06-29 |
| 5217830 | Method of fabricating phase shifting reticles using ion implantation | — | 1993-06-08 |
| 5210472 | Flat panel display in which low-voltage row and column address signals control a much pixel activation voltage | Stephen L. Casper | 1993-05-11 |
| 5208125 | Phase shifting reticle fabrication using ion implantation | Randal W. Chance | 1993-05-04 |
| 5205770 | Method to form high aspect ratio supports (spacers) for field emission display using micro-saw technology | Trung T. Doan, David A. Cathey, J. Brett Rolfson | 1993-04-27 |
| 5194753 | Method of preventing storage node to storage node shorts in fabrication of memory integrated circuitry having stacked capacitors and stacked capacitor memory integrated circuits | Howard E. Rhodes | 1993-03-16 |
| 5186670 | Method to form self-aligned gate structures and focus rings | Trung T. Doan, David A. Cathey, J. Brett Rolfson | 1993-02-16 |
| 5177027 | Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path | Randal W. Chance, D. Mark Durcan, Pierre C. Fazan, Fernando Gonzalez, Gordon A. Haller | 1993-01-05 |
| 5149668 | Method of preventing storage node to storage node shorts in fabrication of memory integrated circuitry having stacked capacitors and stacked capacitor memory integrated circuits | Howard E. Rhodes | 1992-09-22 |
| 5134085 | Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories | Brent Gilgen, Joseph Karniewicz, Anthony M. McQueen | 1992-07-28 |
| 5126290 | Method of making memory devices utilizing one-sided ozone teos spacers | Ruojia Lee | 1992-06-30 |
| 5110754 | Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM | Kevin G. Duesman, Eugene H. Cloud | 1992-05-05 |
| 5087951 | Semiconductor memory device transistor and cell structure | Randal W. Chance | 1992-02-11 |
| 5073518 | Process to mechanically and plastically deform solid ductile metal to fill contacts of conductive channels with ductile metal and process for dry polishing excess metal from a semiconductor wafer | Trung T. Doan, Mark E. Tuttle | 1991-12-17 |
| 5069747 | Creation and removal of temporary silicon dioxide structures on an in-process integrated circuit with minimal effect on exposed, permanent silicon dioxide structures | David A. Cathey, Mark E. Tuttle, Ruojia Lee | 1991-12-03 |
| 5057449 | Process for creating two thicknesses of gate oxide within a dynamic random access memory | Fernando Gonzalez, Joseph Karniewicz | 1991-10-15 |
| 5032530 | Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants | Randal W. Chance, Ward Parkinson | 1991-07-16 |
| 5032545 | Process for preventing a native oxide from forming on the surface of a semiconductor material and integrated circuit capacitors produced thereby | Trung T. Doan | 1991-07-16 |
| 5026657 | Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions | Ruojia Lee, Fernando Gonzalez, Joseph Karniewicz, Pierre C. Fazan | 1991-06-25 |
| 5021353 | Split-polysilicon CMOS process incorporating self-aligned silicidation of conductive regions | Dermot M. Durcan, Trung T. Doan, Gordon A. Haller, Mark E. Tuttle | 1991-06-04 |
| 5013680 | Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography | Randal W. Chance, D. Mark Durcan, Ruojia Lee, Charles H. Dennison, Yauh-Ching Liu +3 more | 1991-05-07 |
| 4999160 | Aluminum alloy containing copper, silicon and titanium for VLSI devices | Trung T. Doan | 1991-03-12 |
| 4957878 | Reduced mask manufacture of semiconductor memory devices | Randal W. Chance | 1990-09-18 |
| 4924442 | Pull up circuit for digit lines in a semiconductor memory | Zhitong Chen, Gary M. Johnson, Ward Parkinson, Wen-Foo Chern, Thomas Trent | 1990-05-08 |