Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7096446 | Hierarchical semiconductor design | — | 2006-08-22 |
| 6922659 | Parameter population of cells of a hierarchical semiconductor structure via file relation | — | 2005-07-26 |
| 6449757 | Hierarchical semiconductor design | — | 2002-09-10 |
| 6404018 | Static memory cell and method of manufacturing a static memory cell | Jeff Zhiqiang Wu | 2002-06-11 |
| 6184539 | Static memory cell and method of forming static memory cell | Jeff Zhiqiang Wu | 2001-02-06 |
| 6140685 | Static memory cell and method of manufacturing a static memory cell | Jeff Zhiqiang Wu | 2000-10-31 |
| 5976926 | Static memory cell and method of manufacturing a static memory cell | Jeff Zhiqiang Wu | 1999-11-02 |
| 5780906 | Static memory cell and method of manufacturing a static memory cell | Jeff Zhiqiang Wu | 1998-07-14 |
| 5770497 | Method of manufacturing a novel static memory cell having a tunnel diode | Jeff Zhiqiang Wu | 1998-06-23 |
| 5757051 | Static memory cell and method of manufacturing a static memory cell | Jeff Zhiqiang Wu | 1998-05-26 |
| 5672536 | Method of manufacturing a novel static memory cell having a tunnel diode | Jeff Zhiqiang Wu | 1997-09-30 |
| 5629546 | Static memory cell and method of manufacturing a static memory cell | Jeff Zhiqiang Wu | 1997-05-13 |
| 5135882 | Technique for forming high-value inter-nodal coupling resistance for rad-hard applications in a double-poly, salicide process using local interconnect | — | 1992-08-04 |
| 5134085 | Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories | Brent Gilgen, Tyler Lowrey, Anthony M. McQueen | 1992-07-28 |
| 5057449 | Process for creating two thicknesses of gate oxide within a dynamic random access memory | Tyler Lowrey, Fernando Gonzalez | 1991-10-15 |
| 5030585 | Split-polysilicon CMOS DRAM process incorporating selective self-aligned silicidation of conductive regions and nitride blanket protection of N-channel regions during P-channel gate spacer formation | Fernando Gonzalez | 1991-07-09 |
| 5026657 | Split-polysilicon CMOS DRAM process incorporating self-aligned silicidation of the cell plate, transistor gates, and N+ regions | Ruojia Lee, Tyler Lowrey, Fernando Gonzalez, Pierre C. Fazan | 1991-06-25 |