Issued Patents All Time
Showing 251–275 of 303 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5424975 | Reference circuit for a non-volatile ferroelectric memory | Wayne Kinney | 1995-06-13 |
| 5405788 | Method for forming and tailoring the electrical characteristics of semiconductor devices | Monte Manning, Charles H. Dennison, Howard E. Rhodes | 1995-04-11 |
| 5405791 | Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers | Aftab Ahmad | 1995-04-11 |
| 5376577 | Method of forming a low resistive current path between a buried contact and a diffusion region | Martin C. Roberts | 1994-12-27 |
| 5372973 | Method to form self-aligned gate structures around cold cathode emitter tips using chemical mechanical polishing technology | Trung T. Doan, J. Brett Rolfson, David A. Cathey | 1994-12-13 |
| 5360992 | Two piece assembly for the selection of pinouts and bond options on a semiconductor device | Alan R. Reinberg, Kevin D. Martin | 1994-11-01 |
| 5357172 | Current-regulated field emission cathodes for use in a flat panel display in which low-voltage row and column address signals control a much higher pixel activation voltage | John Lee, Stephen L. Casper | 1994-10-18 |
| 5346836 | Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects | Monte Manning, Steve V. Cole | 1994-09-13 |
| 5332682 | Local encroachment reduction | — | 1994-07-26 |
| 5331196 | One-time, voltage-programmable, logic element | Ruojia Lee | 1994-07-19 |
| 5329207 | Field emission structures produced on macro-grain polysilicon substrates | David A. Cathey, J. Brett Rolfson, Trung T. Doan | 1994-07-12 |
| 5328810 | Method for reducing, by a factor or 2.sup.-N, the minimum masking pitch of a photolithographic process | Randal W. Chance, David A. Cathey | 1994-07-12 |
| 5324681 | Method of making a 3-dimensional programmable antifuse for integrated circuits | Kevin G. Duesman, Eugene H. Cloud | 1994-06-28 |
| 5306951 | Sidewall silicidation for improved reliability and conductivity | Roger Lee, Fernando Gonzalez | 1994-04-26 |
| 5292681 | Method of processing a semiconductor wafer to form an array of nonvolatile memory devices employing floating gate transistors and peripheral area having CMOS transistors | Roger Lee, Fernando Gonzalez, J. Dennis Keller | 1994-03-08 |
| 5286993 | One-sided ozone TEOS spacer | Ruojia Lee | 1994-02-15 |
| 5283204 | Method of forming passivation oxidation for improving cell leakage and cell area | Howard E. Rhodes | 1994-02-01 |
| 5272367 | Fabrication of complementary n-channel and p-channel circuits (ICs) useful in the manufacture of dynamic random access memories (drams) | Charles H. Dennison | 1993-12-21 |
| 5259799 | Method to form self-aligned gate structures and focus rings | Trung T. Doan, David A. Cathey, J. Brett Rolfson | 1993-11-09 |
| 5258096 | Method of forming local etch stop landing pads for simultaneous, self-aligned dry etching of contact vias with various depths | Gurtej S. Sandhu, Donwon Park | 1993-11-02 |
| 5252504 | Reverse polysilicon CMOS fabrication | Fernando Gonzalez, Ruojia Lee | 1993-10-12 |
| 5244842 | Method of increasing capacitance by surface roughening in semiconductor wafer processing | David A. Cathey, Mark E. Tuttle | 1993-09-14 |
| 5241496 | Array of read-only memory cells, eacch of which has a one-time, voltage-programmable antifuse element constructed within a trench shared by a pair of cells | Ruojia Lee | 1993-08-31 |
| 5233206 | Double digitlines for multiple programming of prom applications and other anti-fuse circuit element applications | Roger Lee, D. Mark Durcan | 1993-08-03 |
| 5232549 | Spacers for field emission display fabricated via self-aligned high energy ablation | David A. Cathey, Chris C. Yu, Trung T. Doan, J. Brett Rolfson | 1993-08-03 |