Issued Patents All Time
Showing 26–50 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8216949 | Method for integrated circuit fabrication using pitch multiplication | Gurtej S. Sandhu, Luan C. Tran, William T. Rericha, D. Mark Durcan | 2012-07-10 |
| 8207614 | Methods for forming arrays of small, closely spaced features | Gurtej S. Sandhu | 2012-06-26 |
| 8207576 | Pitch reduced patterns relative to photolithography features | Luan C. Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah +7 more | 2012-06-26 |
| 8183138 | Methods for forming nanodots and/or a patterned material during the formation of a semiconductor device | Krupakar M. Subramanian | 2012-05-22 |
| 8119535 | Pitch reduced patterns relative to photolithography features | Luan C. Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah +7 more | 2012-02-21 |
| 8048812 | Pitch reduced patterns relative to photolithography features | Luan C. Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah +7 more | 2011-11-01 |
| 8011090 | Method for forming and planarizing adjacent regions of an integrated circuit | David H. Wells, Baosuo Zhou, Krupakar M. Subramanian | 2011-09-06 |
| 7910483 | Trim process for critical dimension control for integrated circuits | Krupaker Murali Subramanian, Baosuo Zhou | 2011-03-22 |
| 7910288 | Mask material conversion | Gurtej S. Sandhu | 2011-03-22 |
| 7857982 | Methods of etching features into substrates | Gurtej S. Sandhu, Aaron R. Wilson, Tony Schrock | 2010-12-28 |
| 7718540 | Pitch reduced patterns relative to photolithography features | Luan C. Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah +7 more | 2010-05-18 |
| 7687408 | Method for integrated circuit fabrication using pitch multiplication | Gurtej S. Sandhu, Luan C. Tran, William T. Rericha, D. Mark Durcan | 2010-03-30 |
| 7662299 | Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same | Krupakar M. Subramanian | 2010-02-16 |
| 7662718 | Trim process for critical dimension control for integrated circuits | Krupakar M. Subramanian, Baosuo Zhou | 2010-02-16 |
| 7651951 | Pitch reduced patterns relative to photolithography features | Luan C. Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah +7 more | 2010-01-26 |
| 7629693 | Method for integrated circuit fabrication using pitch multiplication | Gurtej S. Sandhu, Luan C. Tran, William T. Rericha, D. Mark Durcan | 2009-12-08 |
| 7611980 | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures | David H. Wells | 2009-11-03 |
| 7563723 | Critical dimension control for integrated circuits | David K. Hwang, Robert Veltrop | 2009-07-21 |
| 7547599 | Multi-state memory cell | Gurtej S. Sandhu | 2009-06-16 |
| 7547640 | Method for integrated circuit fabrication using pitch multiplication | Gurtej S. Sandhu, Luan C. Tran, William T. Rericha, D. Mark Durcan | 2009-06-16 |
| 7507672 | Plasma etching system and method | Brad J. Howard, Kevin G. Donohoe | 2009-03-24 |
| 7473645 | Method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate | Krupakar M. Subramanian | 2009-01-06 |
| 7429536 | Methods for forming arrays of small, closely spaced features | Gurtej S. Sandhu | 2008-09-30 |
| 7393789 | Protective coating for planarization | David H. Wells, Baosuo Zhou, Krupakar M. Subramanian | 2008-07-01 |
| 7291563 | Method of etching a substrate; method of forming a feature on a substrate; and method of depositing a layer comprising silicon, carbon, and fluorine onto a semiconductor substrate | Krupakar M. Subramanian | 2007-11-06 |