Issued Patents All Time
Showing 25 most recent of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11889680 | Integrated assemblies and methods of forming integrated assemblies | Richard J. Hill, Gurtej S. Sandhu | 2024-01-30 |
| 11777036 | Integrated assemblies and methods of forming integrated assemblies | Richard J. Hill, Gurtej S. Sandhu | 2023-10-03 |
| 11670707 | Integrated assemblies and methods of forming integrated assemblies | John F. Kaeding, Richard J. Hill, Scott E. Sills | 2023-06-06 |
| 11393920 | Integrated assemblies and methods of forming integrated assemblies | John F. Kaeding, Richard J. Hill, Scott E. Sills | 2022-07-19 |
| 10643906 | Methods of forming a transistor and methods of forming an array of memory cells | John Smythe, Haitao Liu, Richard J. Hill, Deepak Chandra Pandey | 2020-05-05 |
| 9263095 | Memory having buried digit lines and methods of making the same | Kunal R. Parekh, Wen-Kuei Huang, Kuo-Chen Wang, Ching-Kai Lin | 2016-02-16 |
| 9219001 | Methods of forming semiconductor devices having recesses | Aaron R. Wilson, Larson Lindholm | 2015-12-22 |
| 9041086 | Methods of forming vertical field effect transistors, vertical field effect transistors, and DRAM cells | Larson Lindholm | 2015-05-26 |
| 8716116 | Method of forming a DRAM array of devices with vertically integrated recessed access device and digitline | Kunal R. Parekh, Ceredig Roberts, Thy Tran, Jim A. Jozwiak | 2014-05-06 |
| 8691656 | Methods of forming an interconnect between a substrate bit line contact and a bit line in DRAM | Brett W. Busch, F. Daniel Gealy | 2014-04-08 |
| 8497530 | Semiconductor structures including dual fins | Aaron R. Wilson, Larson Lindholm | 2013-07-30 |
| 8497541 | Memory having buried digit lines and methods of making the same | Kunal R. Parekh, Wen-Kuei Huang, Kuo-Chen Wang, Ching-Kai Lin | 2013-07-30 |
| 8211763 | Methods of forming vertical field effect transistors, vertical field effect transistors, and DRAM cells | Larson Lindholm | 2012-07-03 |
| 8178911 | Semiconductor device having reduced sub-threshold leakage | Larson Lindholm | 2012-05-15 |
| 8138526 | Semiconductor structures including dual fins | Aaron R. Wilson, Larson Lindholm | 2012-03-20 |
| 8030168 | Methods of forming DRAM memory cells | Brett W. Busch, F. Daniel Gealy | 2011-10-04 |
| 8022473 | Semiconductor device having reduced sub-threshold leakage | Larson Lindholm | 2011-09-20 |
| 7948030 | Semiconductor constructions of memory devices with different sizes of GateLine trenches | Larson Lindholm, Aaron R. Wilson | 2011-05-24 |
| 7935999 | Memory device | Gordon A. Haller, Sanh D. Tang, Ceredig Roberts | 2011-05-03 |
| 7910971 | Methods of forming vertical field effect transistors, vertical field effect transistors, and dram cells | Larson Lindholm | 2011-03-22 |
| 7897465 | Semiconductor device having reduced sub-threshold leakage | Larson Lindholm | 2011-03-01 |
| 7879659 | Methods of fabricating semiconductor devices including dual fin structures | Aaron R. Wilson, Larson Lindholm | 2011-02-01 |
| 7808041 | Semiconductor constructions of memory device with different depth gate line trenches | Larson Lindholm, Aaron R. Wilson | 2010-10-05 |
| 7696568 | Semiconductor device having reduced sub-threshold leakage | Larson Lindholm | 2010-04-13 |
| 7687342 | Method of manufacturing a memory device | Gordon A. Haller, Sanh D. Tang, Ceredig Roberts | 2010-03-30 |