Issued Patents All Time
Showing 26–50 of 164 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7340706 | Method and system for analyzing the quality of an OPC mask | Ilya Golubtsov, Stanislav V. Aleshin, Sergei Rodin, Marina Medvedeva, Sergey V. Uzhakov +2 more | 2008-03-04 |
| 7315993 | Verification of RRAM tiling netlist | Andrey Nikitin, Alexander E. Andreev | 2008-01-01 |
| 7305597 | System and method for efficiently testing a large random access memory space | Alexander E. Andreev | 2007-12-04 |
| 7305593 | Memory mapping for parallel turbo decoding | Alexander E. Andreev, Anatoli Bolotov | 2007-12-04 |
| 7231383 | Search engine for large-width data | Alexander E. Andreev, Anatoli Bolotov | 2007-06-12 |
| 7216278 | Method and BIST architecture for fast memory testing in platform-based integrated circuit | Alexander E. Andreev, Anatoli Bolotov | 2007-05-08 |
| 7200826 | RRAM memory timing learning tool | Alexandre Andreev, Andrey Nikitin | 2007-04-03 |
| 7181563 | FIFO memory with single port memory modules for allowing simultaneous read and write operations | Alexander E. Andreev, Anatoli Bolotov | 2007-02-20 |
| 7168052 | Yield driven memory placement system | Alexander E. Andreev, Andrey Nikitin | 2007-01-23 |
| 7155688 | Memory generation and placement | Alexandre Andreev, Ilya V. Neznanov, Andrey Nikitin, Igor Vikhliantsev | 2006-12-26 |
| 7111264 | Process and apparatus for fast assignment of objects to a rectangle | Alexander E. Andreev, Andrey Nikitin | 2006-09-19 |
| 7096413 | Decomposer for parallel turbo decoding, process and integrated circuit | Alexander E. Andreev, Vojislav Vukovic | 2006-08-22 |
| 7065606 | Controller architecture for memory mapping | Alexander E. Andreev, Igor Vikhliantsev | 2006-06-20 |
| 7050582 | Pseudo-random one-to-one circuit synthesis | Alexander E. Andreev, Igor Vikhliantsev | 2006-05-23 |
| 7035844 | FFS search and edit pipeline separation | Alexander E. Andreev | 2006-04-25 |
| 7028274 | RRAM backend flow | Alexander E. Andreev, Ivan Pavisic, Vojislav Vukovic | 2006-04-11 |
| 7003510 | Table module compiler equivalent to ROM | Alexander E. Andreev | 2006-02-21 |
| 6988252 | Universal gates for ICs and transformation of netlists for their implementation | Alexander E. Andreev | 2006-01-17 |
| 6941314 | User selectable editing protocol for fast flexible search engine | Alexander E. Andreev | 2005-09-06 |
| 6928591 | Fault repair controller for redundant memory integrated circuits | Mikhail I. Grinchuk, Ghasi R. Agrawal | 2005-08-09 |
| 6901571 | Timing-driven placement method utilizing novel interconnect delay model | Dusan Petranovic, Ivan Pavisic | 2005-05-31 |
| 6898780 | Method and system for constructing a hierarchy-driven chip covering for optical proximity correction | Evgueny E. Egorov, Stanislav V. Aleshin | 2005-05-24 |
| 6886088 | Memory that allows simultaneous read requests | Egor A. Andreev, Anatoli Bolotov, Alexander E. Andreev | 2005-04-26 |
| 6845495 | Multidirectional router | Alexandre Andreev, Elyar E. Gasanov | 2005-01-18 |
| 6842750 | Symbolic simulation driven netlist simplification | Alexander E. Andreev | 2005-01-11 |