Issued Patents All Time
Showing 1–25 of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7913125 | BISR mode to test the redundant elements and regular functional memory to avoid test escapes | Mukesh K. Puri | 2011-03-22 |
| 7640152 | Accurate pin-based memory power model using arc-based characterization | Jia-Lih J. Chen, Naveen Gupta | 2009-12-29 |
| 7536611 | Hard BISR scheme allowing field repair and usage of reliability controller | Mukesh K. Puri, Tuan Phan | 2009-05-19 |
| 7493541 | Method and system for performing built-in-self-test routines using an accumulator to store fault information | Mukesh K. Puri, William Schwarz | 2009-02-17 |
| 7376541 | Accurate pin-based memory power model using arc-based characterization | Jia-Lih J. Chen, Naveen Gupta | 2008-05-20 |
| 7272814 | Reconfiguring a RAM to a ROM using layers of metallization | Allen Faber | 2007-09-18 |
| 7260700 | Method and apparatus for separating native, functional and test configurations of memory | Willie K. C. Chan | 2007-08-21 |
| 7260758 | Method and system for performing built-in self-test routines using an accumulator to store fault information | Mukesh K. Puri, William Schwarz | 2007-08-21 |
| 7185243 | Testing implementation suitable for built-in self-repair (BISR) memories | Mukesh K. Puri, Thompson W. Crosby | 2007-02-27 |
| 7180819 | Converting dual port memory into 2 single port memories | — | 2007-02-20 |
| 7076699 | Method for testing semiconductor devices having built-in self repair (BISR) memory | Mukesh K. Puri, William Schwarz | 2006-07-11 |
| 6928591 | Fault repair controller for redundant memory integrated circuits | Mikhail I. Grinchuk, Ranko Scepanovic | 2005-08-09 |
| 6928598 | Scan method for built-in-self-repair (BISR) | Mukesh K. Puri | 2005-08-09 |
| 6898143 | Sharing fuse blocks between memories in hard-BISR | Mukesh K. Puri | 2005-05-24 |
| 6870782 | Row redundancy memory repair scheme with shift to eliminate timing penalty | Sifang Wu, Kevin LeClair | 2005-03-22 |
| 6871297 | Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories | Mukesh K. Puri | 2005-03-22 |
| 6643204 | Self-time scheme to reduce cycle time for memories | — | 2003-11-04 |
| 6640321 | Built-in self-repair of semiconductor memory with redundant row testing using background pattern | Johnnie A. Huang | 2003-10-28 |
| 6507524 | Integrated circuit memory having column redundancy | Thomas R. Wik | 2003-01-14 |
| 6483754 | Self-time scheme to reduce cycle time for memories | — | 2002-11-19 |
| 6438046 | System and method for providing row redundancy with no timing penalty for built-in-self-repair (BISR) in high density memories | — | 2002-08-20 |
| 6404700 | Low power high density asynchronous memory architecture | — | 2002-06-11 |
| 6370078 | Way to compensate the effect of coupling between bitlines in a multi-port memories | Thomas R. Wik | 2002-04-09 |
| 6366508 | Integrated circuit memory having column redundancy with no timing penalty | Jerry K. Tanaka | 2002-04-02 |
| 6341092 | Designing memory for testability to support scan capability in an asic design | — | 2002-01-22 |