| 9780722 |
Low-cost efficient solar panels |
— |
2017-10-03 |
| 9762261 |
Error detection and correction in ternary content addressable memory (TCAM) |
Michael A. Zampaglione |
2017-09-12 |
| 9529669 |
Error detection and correction in binary content addressable memory (BCAM) |
Michael A. Zampaglione |
2016-12-27 |
| 8921680 |
Low-cost solar collector |
— |
2014-12-30 |
| 7746921 |
Resonant digital data transmission |
— |
2010-06-29 |
| 7603509 |
Crossbar switch with grouped inputs and outputs |
— |
2009-10-13 |
| 7557618 |
Conditioning logic technology |
— |
2009-07-07 |
| 6507524 |
Integrated circuit memory having column redundancy |
Ghasi R. Agrawal |
2003-01-14 |
| 6370078 |
Way to compensate the effect of coupling between bitlines in a multi-port memories |
Ghasi R. Agrawal |
2002-04-09 |
| 6233197 |
Multi-port semiconductor memory and compiler having capacitance compensation |
Ghasi R. Agrawal |
2001-05-15 |
| 6137716 |
Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell |
— |
2000-10-24 |
| 6018480 |
Method and system which permits logic signal routing over on-chip memories |
Myron Buer, Robin H. Passow, Ken Redding |
2000-01-25 |
| 5987632 |
Method of testing memory operations employing self-repair circuitry and permanently disabling memory locations |
V. Swamy Irrinki |
1999-11-16 |
| 5982659 |
Memory cell capable of storing more than two logic states by using different via resistances |
V. Swamy Irrinki, Raymond Leung, Ashok K. Kapoor, Alex Owens |
1999-11-09 |
| 5903505 |
Method of testing memory refresh operations wherein subthreshold leakage current may be set to near worst-case conditions |
Tuan Phan, Thien Trieu |
1999-05-11 |
| 5867423 |
Memory circuit and method for multivalued logic storage by process variations |
Ashok K. Kapoor, Alex Owens, Raymond Leung, V. Swamy Irrinki |
1999-02-02 |
| 5847990 |
Ram cell capable of storing 3 logic states |
V. Swamy Irrinki, Ashok K. Kapoor, Raymond Leung, Alex Owens |
1998-12-08 |
| 5841695 |
Memory system using multiple storage mechanisms to enable storage and retrieval of more than two states in a memory cell |
— |
1998-11-24 |
| 5808932 |
Memory system which enables storage and retrieval of more than two states in a memory cell |
V. Swamy Irrinki, Ashok K. Kapoor, Raymond Leung, Alex Owens |
1998-09-15 |
| 5796650 |
Memory circuit including write control unit wherein subthreshold leakage may be reduced |
Shahryar Aryani |
1998-08-18 |
| 5784328 |
Memory system including an on-chip temperature sensor for regulating the refresh rate of a DRAM array |
V. Swamy Irrinki, Ashok K. Kapoor, Raymond Leung, Alex Owens |
1998-07-21 |
| 5761110 |
Memory cell capable of storing more than two logic states by using programmable resistances |
V. Swamy Irrinki, Ashok K. Kapoor, Raymond Leung, Alex Owens |
1998-06-02 |
| 5559463 |
Low power clock circuit |
John S. Denker, Alexander G. Dickinson, Alan Kramer |
1996-09-24 |
| 5506519 |
Low energy differential logic gate circuitry having substantially invariant clock signal loading |
Steven C. Avery, John S. Denker, Alexander G. Dickinson, Alan Kramer |
1996-04-09 |
